2008 Asia and South Pacific Design Automation Conference最新文献_第7页

An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators 一个有效的，完全非线性的，可变感知的非蒙特卡罗产率估计程序，应用于SRAM单元和环形振荡器

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484052

Chenjie Gu, J. Roychowdhury

{"title":"An efficient, fully nonlinear, variability-aware non-monte-carlo yield estimation procedure with applications to SRAM cells and ring oscillators","authors":"Chenjie Gu, J. Roychowdhury","doi":"10.1109/ASPDAC.2008.4484052","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484052","url":null,"abstract":"Failures and yield problems due to parameter variations have become a significant issue for sub-90-nm technologies. As a result, CAD algorithms and tools that provide designers the ability to estimate the effects of variability quickly and accurately are being urgently sought. The need for such tools is particularly acute for static RAM (SRAM) cells and integrated oscillators, for such circuits require expensive and high-accuracy simulation during design. We present a novel technique for fast computation of parametric yield. The technique is based on efficient, adaptive geometric calculation of probabilistic hypervolumes subtended by the boundary separating pass/fail regions in parameter space. A key feature of the method is that it is far more efficient than Monte-Carlo, while at the same time achieving better accuracy in typical applications. The method works equally well with parameters specified as corners, or with full statistical distributions; importantly, it scales well when many parameters are varied. We apply the method to an SRAM cell and a ring oscillator and provide extensive comparisons against full Monte-Carlo, demonstrating speedups of 100-1000 times.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124323763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

A fast two-pass HDL simulation with on-demand dump 一个快速的双通道HDL仿真与按需转储

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483987

Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyung-Seok Kim, Dusung Kim, Jae-Beom Kim, Byeong Min, Kyumyung Choi, M. Ciesielski, Seiyang Yang

{"title":"A fast two-pass HDL simulation with on-demand dump","authors":"Kyuho Shim, Young-Rae Cho, Namdo Kim, Hyuncheol Baik, Kyung-Seok Kim, Dusung Kim, Jae-Beom Kim, Byeong Min, Kyumyung Choi, M. Ciesielski, Seiyang Yang","doi":"10.1109/ASPDAC.2008.4483987","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483987","url":null,"abstract":"Simulation-based functional verification is characterized by two inherently conflicting targets: the signal visibility and simulation performance. Achieving a proper trade-off between these two targets is of paramount importance. Even though HDL simulators are the most widely used verification platform at the RTL and gate level, their major drawback is the low performance in verifying complex SOCs, especially when the high visibility over the design under verification is required. This paper presents a new, fast simulation method as an effective way to achieve both high simulation speed and full signal visibility. It is based on an original two-pass simulation approach. During the 1st pass, with the simulation running at full speed, a set of design states is saved periodically at predetermined checkpoints. During the 2nd pass, another simulation is performed, using any of saved checkpoints and providing 100% signal visibility for debugging. Our method differs from the traditional simulation snapshot approach in the amount and the way the design state is saved. Experimental results show significant speed-up compared to existing traditional simulation methods while maintaining 100% visibility.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133705265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Design space exploration for a coarse grain accelerator 粗粮加速器的设计空间探索

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484039

Farhad Mehdipour, Hamid Noori, M. S. Zamani, Koji Inoue, K. Murakami

引用次数: 4

Variability-driven module selection with joint design time optimization and post-silicon tuning 可变驱动的模块选择与联合设计时间优化和后硅调谐

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483963

Feng Wang, Xiaoxia Wu, Yuan Xie

{"title":"Variability-driven module selection with joint design time optimization and post-silicon tuning","authors":"Feng Wang, Xiaoxia Wu, Yuan Xie","doi":"10.1109/ASPDAC.2008.4483963","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483963","url":null,"abstract":"Increasing delay and power variation are significant challenges to the designers as technology scales to the deep sub-micron (DSM) regime. Traditional module selection techniques in high level synthesis use worst case delay/power information to perform the optimization, and therefore may be too pessimistic such that extra resources are used to guarantee design requirements. Parametric yield, which is defined as the probability of the synthesized hardware meeting the performance/power constraints, can be used to guide design space exploration. The parametric yield can be effectively improved by combining both design-time variation-aware optimization and post silicon tuning techniques (such as adaptive body biasing (ABB)). In this paper, we propose a module selection algorithm that combines design-time optimization with post- silicon tuning (using ABB) to maximize design yield. A variation-aware module selection algorithm based on efficient performance and power yield gradient computation is developed. The post silicon optimization is formulated as an efficient sequential conic program to determine the optimal body bias distribution, which in turn affects design-time module selection. The experiment results show that significant yield can be achieved compared to traditional worst-case driven module selection technique. To the best of our knowledge, this is the first variability-driven high level synthesis technique that considers post-silicon tuning during design time optimization.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124464869","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 46

A fast incremental clock skew scheduling algorithm for slack optimization 一种用于松弛优化的快速增量时钟偏差调度算法

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484000

Kui Wang, Hao Fang, Hu Xu, Xu Cheng

引用次数: 3

An innovative Steiner tree based approach for polygon partitioning 一种创新的基于斯坦纳树的多边形划分方法

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483974

Yongqiang Lyu, Qing Su, J. Kawa

引用次数: 3

Non-Gaussian Statistical Timing models of die-to-die and within-die parameter variations for full chip analysis 用于全芯片分析的模间和模内参数变化的非高斯统计时序模型

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483961

Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya

引用次数: 6

Determination of optimal polynomial regression function to decompose on-die systematic and random variations 确定最优多项式回归函数分解系统和随机变化

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484006

Takashi Sato, Hiroyuki Ueyama, N. Nakayama, K. Masu

引用次数: 11

Analog circuit simulation using range arithmetics 模拟电路仿真使用距离算法

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484053

D. Grabowski, M. Olbrich, E. Barke

引用次数: 44

An MILP-based wire spreading algorithm for PSM-aware layout modification 一种基于milp的psm感知布局修改的导线扩展算法

2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483975

Ming-Chao Tsai, Yung-Chia Lin, Ting-Chi Wang

引用次数: 3