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2008 Asia and South Pacific Design Automation Conference最新文献

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A delay model for interconnect trees based on ABCD matrix 基于ABCD矩阵的互连树延迟模型
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484004
Guofei Zhou, L. Su, Depeng Jin, Lieguang Zeng
{"title":"A delay model for interconnect trees based on ABCD matrix","authors":"Guofei Zhou, L. Su, Depeng Jin, Lieguang Zeng","doi":"10.1109/ASPDAC.2008.4484004","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484004","url":null,"abstract":"The accuracy of interconnect delay estimations can be improved by the method presented in this paper, in which the first two moments are obtained with ABCD matrix and a stable model to incorporate effects of transport delay into the delay estimate is developed. Simulation results show that the method share the same accuracy with traditional methods when rise time delay is much longer than transport delay and more accurate when the two are of the same order.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"383 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115300556","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Robust test generation for power supply noise induced path delay faults 电源噪声引起的路径延迟故障鲁棒性测试生成
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484033
Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li
{"title":"Robust test generation for power supply noise induced path delay faults","authors":"Xiang Fu, Huawei Li, Yu Hu, Xiaowei Li","doi":"10.1109/ASPDAC.2008.4484033","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484033","url":null,"abstract":"In deep sub-micron designs, the delay caused by power supply noise (PSN) can no longer be ignored. A PSN-induced path delay fault (PSNPDF) model is proposed in this paper, and should be tested to enhance chip quality. Based on precise timing analysis, we also propose a robust test generation technique for PSNPDF. Concept of timing window is introduced into the PSNPDF model. If two devices in the same feed region simultaneously switch in the same direction, the current waveform of the two devices will have an overlap and excessive PSN will be produced. Experimental results on ISCAS'89 circuits showed test generation can be finished in a few seconds.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122796360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond 协同物理合成可制造性和可变性在45纳米及以上的设计
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483945
D. Pan, Minsik Cho
{"title":"Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond","authors":"D. Pan, Minsik Cho","doi":"10.1109/ASPDAC.2008.4483945","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483945","url":null,"abstract":"Nanometer IC designs are increasingly challenged by manufacturing closure, i.e., being fabricated with high product yield, mainly due to aggressive technology scaling and increasing process/environmental variations. Realizing the criticality of addressing manufacturability for higher yield and tolerance to variations during design, there has been a surge of research activities recently from both academia and industry. In this paper, we will survey the key activities in synergistic physical synthesis and shed lights on some of the future research directions.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125286847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Duo-binary circular turbo decoder based on border metric encoding for WiMAX 基于边界度量编码的WiMAX双二进制圆形turbo解码器
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483918
Ji-Hoon Kim, I. Park
{"title":"Duo-binary circular turbo decoder based on border metric encoding for WiMAX","authors":"Ji-Hoon Kim, I. Park","doi":"10.1109/ASPDAC.2008.4483918","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483918","url":null,"abstract":"This paper presents a duo-binary circular turbo decoder based on border metric encoding. With the proposed method, the memory size for branch memory is reduced by half and the dummy calculation is removed at the cost of the small-sized memory which holds the encoded border metrics. Based on the proposed SISO decoder and the dedicated hardware interleaver, a duo-binary circular turbo decoder is designed for the WiMAX standard using a 0.13 mum CMOS process, which can support 24.26 Mbps at 200 MHz.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126267727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension 可重构系统中热传感器的优化配置与放置及其实用推广
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484042
Byunghyun Lee, Taewhan Kim
{"title":"Optimal allocation and placement of thermal sensors for reconfigurable systems and its practical extension","authors":"Byunghyun Lee, Taewhan Kim","doi":"10.1109/ASPDAC.2008.4484042","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484042","url":null,"abstract":"A dynamic monitoring of thermal behavior of hardware resources using thermal sensors is very important to maintain the operation of systems safe and reliable. This work proposes an effective solution to the problem of thermal sensor allocation and placement for reconfigurable systems at the post-manufacturing stage. Specifically, we define the sensor allocation and placement problem (SAPP), and propose a solution which formulates SAPP into the unate-covering problem (UCP) and solves it optimally. We then provide an extended solution to handle a practical design issue where the hardware resources for the sensor implementation on specific array locations have already been used up by the application logic. Experimental results using MCNC benchmarks show that our proposed technique uses 19.7% less number of sensors to monitor hotspots on the average than that used by the bisection based (Mukherjee et al., 2006) approaches.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"443 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125763856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Investigation of diffusion rounding for post-lithography analysis 光刻后分析中扩散舍入的研究
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483998
Puneet Gupta, A. Kahng, Youngmin Kim, Saumil Shah, D. Sylvester
{"title":"Investigation of diffusion rounding for post-lithography analysis","authors":"Puneet Gupta, A. Kahng, Youngmin Kim, Saumil Shah, D. Sylvester","doi":"10.1109/ASPDAC.2008.4483998","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483998","url":null,"abstract":"Due to aggressive scaling of device feature size to improve circuit performance in the sub-wavelength lithography regime, both diffusion and poly gate shapes are no longer rectilinear. Diffusion rounding occurs most notably where the diffusion shapes are not perfectly rectangular, including common L and T-shaped diffusion layouts to connect to power rails. This paper investigates the impact of the non-rectilinear shape of diffusion (i.e., sloped diffusion or diffusion rounding) on circuit performance (delay and leakage). Simple weighting function models for Ionmiddot and Ioff to account for the diffusion rounding effects are proposed, and compared with TCAD simulation. Our experiments show that diffusion rounding has an asymmetric characteristic for Ioff due to the differing significance of source/drain junctions on device threshold voltage. Therefore, we can model Ionmiddot and Ioff as a function of slope angle and direction. The proposed models match well with TCAD simulation results, with less than 2% and 6% error in Ionmiddot and Ioff, respectively.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129598381","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 1.2GHz delayed clock generator for high-speed microprocessors 用于高速微处理器的1.2GHz延迟时钟发生器
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484068
I. Jung, Moo-young Kim, Chulwoo Kim
{"title":"A 1.2GHz delayed clock generator for high-speed microprocessors","authors":"I. Jung, Moo-young Kim, Chulwoo Kim","doi":"10.1109/ASPDAC.2008.4484068","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484068","url":null,"abstract":"A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13 um CMOS technology occupies only 0.004 mm and operates at variable input frequencies ranging from 625 MHz to 1.2GHz.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124653570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Buffered clock tree synthesis for 3D ICs under thermal variations 热变化下三维集成电路的缓冲时钟树合成
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484003
J. Minz, Xin Zhao, S. Lim
{"title":"Buffered clock tree synthesis for 3D ICs under thermal variations","authors":"J. Minz, Xin Zhao, S. Lim","doi":"10.1109/ASPDAC.2008.4484003","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484003","url":null,"abstract":"In this paper, we study the buffered clock tree synthesis problem under thermal variations for 3D IC technology. Our major contribution is the Balanced Skew Theorem, which provides a theoretical background to efficiently construct a buffered 3D clock tree that minimizes and balances the skew values under two distinct non-uniform thermal profiles. Our clock tree synthesis algorithm named BURITO (buffered clock tree with thermal optimization) first constructs a 3D abstract tree under the wirelength vs via-congestion tradeoff. This abstract tree is then embedded, buffered, and refined under the given non-uniform thermal profiles so that the temperature-dependent skews are minimized and balanced. Experimental results show that our algorithms significantly reduce and perfectly balance clock skew values with minimal wirelength overhead.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130923798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 70
NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks noout:混合分组交换和点对点网络的NoC拓扑生成
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4483953
J. Chan, S. Parameswaran
{"title":"NoCOUT : NoC topology generation with mixed packet-switched and point-to-point networks","authors":"J. Chan, S. Parameswaran","doi":"10.1109/ASPDAC.2008.4483953","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4483953","url":null,"abstract":"Networks-on-chip (NoC) have been widely proposed as the future communication paradigm for use in next-generation system-on-chip. In this paper, we present NoCOUT, a methodology for generating an energy optimized application specific NoC topology which supports both point-to-point and packet-switched networks. The algorithm uses a prohibitive greedy iterative improvement strategy to explore the design space efficiently. A system-level floorplanner is used to evaluate the iterative design improvements and provide feedback on the effects of the topology on wire length. The algorithm is integrated within a NoC synthesis framework with characterized NoC power and area models to allow accurate exploration for a NoC router library. We apply the topology generation algorithm to several test cases including real-world and synthetic communication graphs with both regular and irregular traffic patterns, and varying core sizes. Since the method is iterative, it is possible to start with a known design to search for improvements. Experimental results show that many different applications benefit from a mix of \";on chip networks\"; and \";point-to-point networks\";. With such a hybrid network, we achieve approximately 25% lower energy consumption (with a maximum of 37%) than a state of the art min-cut partition based topology generator for a variety of benchmarks. In addition, the average hop count is reduced by 0.75 hops, which would significantly reduce the network latency.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"24 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120877537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures 同质和异构芯片多处理器体系结构上的节能调度自动化技术
2008 Asia and South Pacific Design Automation Conference Pub Date : 2008-01-21 DOI: 10.1109/ASPDAC.2008.4484026
Sushu Zhang, Karam S. Chatha
{"title":"Automated techniques for energy efficient scheduling on homogeneous and heterogeneous chip multi-processor architectures","authors":"Sushu Zhang, Karam S. Chatha","doi":"10.1109/ASPDAC.2008.4484026","DOIUrl":"https://doi.org/10.1109/ASPDAC.2008.4484026","url":null,"abstract":"We address performance maximization of independent task sets under energy constraint on chip multi-processor (CMP) architectures that support multiple voltage/frequency operating states for each core. We prove that the problem is strongly NP-hard. We propose polynomial time 2-approximation algorithms for homogeneous and heterogeneous CMPs. To the best of our knowledge, our techniques offer the tightest bounds for energy constrained design on CMP architectures. Experimental results demonstrate that our techniques are effective and efficient under various workloads on several CMP architectures.","PeriodicalId":277556,"journal":{"name":"2008 Asia and South Pacific Design Automation Conference","volume":"94 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-01-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120980200","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
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