2012 International Symposium on Electronic System Design (ISED)最新文献_第3页

Design of 4-Bit Array Multiplier Using Multi-wall Carbon Nanotube Interconnects 基于多壁碳纳米管互连的4位阵列倍增器设计

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.19

Debaprasad Das, Sourav Das, H. Rahaman

引用次数: 0

e-SURAKSHAK: A Cyber-Physical Healthcare System with Service Oriented Architecture e-SURAKSHAK:具有面向服务架构的网络物理医疗保健系统

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.66

I. H. Rao, N. A. Amir, Haresh Dagale, J. Kuri

引用次数: 10

A 4-bit Asynchronous Binary Search ADC for Low Power, High Speed Applications 低功耗，高速应用的4位异步二进制搜索ADC

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.18

Sagar Mukherjee, Dipankar Saha, P. Mostafa, S. Chatterjee, C. Sarkar

引用次数: 10

Energy Aware Spectrum Decision Framework for Cognitive Radio Networks 认知无线电网络的能量感知频谱决策框架

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.65

V. Mishra, C. Lau, Syin Chan, Ashish Kumar

引用次数: 12

Multiple Dilution Sample Preparation Using Digital Microfluidic Biochips 利用数字微流控生物芯片制备多重稀释样品

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.73

Sukanta Bhattacharjee, A. Banerjee, B. Bhattacharya

{"title":"Multiple Dilution Sample Preparation Using Digital Microfluidic Biochips","authors":"Sukanta Bhattacharjee, A. Banerjee, B. Bhattacharya","doi":"10.1109/ISED.2012.73","DOIUrl":"https://doi.org/10.1109/ISED.2012.73","url":null,"abstract":"Digital microfluidic (DMF) biochips offer a versatile platform for implementing several laboratory based biochemical protocols. These tiny chips can electrically control the dynamics of nanoliter volume of discrete fluid droplets on an electrode array with desired actuation patterns. One important step in biochemical sample preparation is dilution, where the objective is to prepare a fluid with a desired concentration factor. Bioassays implemented on DMF biochips may require several different concentration values of the same sample. In this paper, we propose a scheme in which a set of different target droplets (target concentration values ranged between 0% and 100%) can be produced using 0% concentration (buffer solution) and 100% concentration (sample/reagent), with an error bounded above by 1/2^(n+1) where concentration values are rounded-off by an n-bit binary fraction. Simulation results show that significant amount of savings in the number of mix-split steps and waste droplets can be achieved in comparison with the repeated use of existing single target based methods for generating multiple concentration factors.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116776135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework 分布式框架下基于细粒度分布式交换机架构的多目标低功耗CDFG调度

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.51

Rajdeep Mukherjee, Priyankar Ghosh, N. Kumar, P. Dasgupta, A. Pal

引用次数: 2

High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers 基于乒乓缓冲器的片上网络高速通用网络接口

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.11

K. Swaminathan, G. Lakshminarayanan, S. Ko

{"title":"High Speed Generic Network Interface for Network on Chip Using Ping Pong Buffers","authors":"K. Swaminathan, G. Lakshminarayanan, S. Ko","doi":"10.1109/ISED.2012.11","DOIUrl":"https://doi.org/10.1109/ISED.2012.11","url":null,"abstract":"Connecting different Intellectual Property (IP) cores with Network on Chip (NoC) router using Network Interface (NI) is a challenging task due to its asynchronous nature and data width. In this paper, a generic high-speed Network Interface for Network on Chip using Ping Pong Buffers is proposed in order to ensure the seamless high throughput between the router and processing core. The proposed scheme uses simple control logic to handle the read and write operations simultaneously in the memory modules. This proposed method is analyzed with the existing Asynchronous First in First Out (FIFO) based NIs with different encoding schemes like One-Hot encoding and Johnson encoding. The optimal depth of the asynchronous FIFOs is calculated based on router frequency, processing element frequency, packet size and flit size at router and processing element using Practical Extraction and Report Language (PERL) and the required Register Transfer Level (RTL) Verilog Hardware Description Language (HDL) and timing constrain is created by Perl scripting itself. The NI is implemented using the asynchronous FIFOs and ping pong - double buffering scheme using Altera Stratix III FPGA. The synthesis results show that the proposed architecture enhances the speed of NI by 30 % when memory depth is 8 and enhances speed by 11% when memory depth is 256.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"138 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114488126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 14

A Design of 6-bit 125-MS/s SAR ADC in 0.13-µm MM/RF CMOS Process 基于0.13µm MM/RF CMOS工艺的6位125 ms /s SAR ADC设计

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.63

R. Rajendran, P. Ramakrishna

引用次数: 2

Identifying Faulty TSVs in 3D Stacked IC during Pre-bond Testing 预键合测试中3D堆叠IC中故障tsv的识别

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.49

S. Roy, S. Chatterjee, C. Giri

引用次数: 9

Signal Stepping Based Multimode Multi-threshold CMOS Technique for Ground Bounce Noise Reduction in Static CMOS Adders 静态CMOS加法器中基于信号步进的多模多阈值CMOS技术

2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.14

Shashikant Sharma, M. Pattanaik, B. Raj

引用次数: 1