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2012 International Symposium on Electronic System Design (ISED)最新文献

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Performance Analysis of Offloading IPsec Processing to Hardware Based Accelerators 将IPsec处理卸载到硬件加速器的性能分析
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.53
Hemant Agrawal, Yashpal Dutta, Sandeep Malik
{"title":"Performance Analysis of Offloading IPsec Processing to Hardware Based Accelerators","authors":"Hemant Agrawal, Yashpal Dutta, Sandeep Malik","doi":"10.1109/ISED.2012.53","DOIUrl":"https://doi.org/10.1109/ISED.2012.53","url":null,"abstract":"Need for Data security over the IP network is raising day by day. One of the security options i.e. IPSec provides security protocols including cipher and authentication to secure network traffic. Algorithms being used in these protocols are highly CPU intensive. Network equipment providers integrate special cryptographic accelerators in SoCs to offload the IPSec processing from CPU. Various level of hardware support is available for IPSec protocol offload, ranging from independent cipher and authentication processing to handling IPSec protocol features in the hardware. This paper covers the comparative analysis of various hardware offload options. The analysis is supported by IPSec protocol offload based implementation and associated test results on one of the Freescale's QorIQ platforms.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128330726","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Synthesis of Toffoli Networks: Status and Challenges Toffoli网络的合成:现状与挑战
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.26
G. Dueck
{"title":"Synthesis of Toffoli Networks: Status and Challenges","authors":"G. Dueck","doi":"10.1109/ISED.2012.26","DOIUrl":"https://doi.org/10.1109/ISED.2012.26","url":null,"abstract":"This paper gives a brief overview of the current trends in reversible logic synthesis. The basic building block for reversible circuits considered here is the multiple-control Toffoli gate. Some approaches to synthesis are reviewed and challenges are explained. Since many practical functions are not reversible, they must be embedded into reversible ones, if they are to be implemented using reversible logic. The complexity of such embeddings is expounded. A two phase synthesis is described were particular attention is devoted to the optimization phase via template matching.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114635145","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults 在对质量故障敏感的嵌入式控制系统中寻找关键部件
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.9
Vishal Shrivastav, Satya Gautam Vadlamudi, P. Chakrabarti, D. Das, Purnendu Sinha
{"title":"Finding Critical Components in Embedded Control Systems Sensitive to Quality-Faults","authors":"Vishal Shrivastav, Satya Gautam Vadlamudi, P. Chakrabarti, D. Das, Purnendu Sinha","doi":"10.1109/ISED.2012.9","DOIUrl":"https://doi.org/10.1109/ISED.2012.9","url":null,"abstract":"Embedded control systems used in safety critical systems need to be robust to quality-faults such as shift, noise, and spikes. Methods for finding counterexamples (quality-faults whose injection leads to violation of fault-tolerance requirements) at an early stage of control system design were proposed in the literature. Given these counterexamples, control design should be improved such that it is quality-fault tolerant. In this paper, we propose an effective methodology for finding critical components in embedded control systems which are sensitive to quality-faults based on the given counterexamples, which is an important step towards improving the control design. Experimental results on the fault-tolerant fuel controller of Simulink library show the efficacy of proposed methodology.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134267356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques 使用不同低功耗技术的FFT/IFFT设计的比较
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.57
Kwen-Siong Chong, J. Chang, I. Ebong, Y. Yilmaz, P. Mazumder
{"title":"Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques","authors":"Kwen-Siong Chong, J. Chang, I. Ebong, Y. Yilmaz, P. Mazumder","doi":"10.1109/ISED.2012.57","DOIUrl":"https://doi.org/10.1109/ISED.2012.57","url":null,"abstract":"Different techniques of power savings in CMOS circuits have been investigated through the years. This work compares the asynchronous approach, the superthreshold approach, and the subthreshold approach in a 128 point FFT processor. The subthreshold design, made in TSMC 65 nm technology, utilizes a 4 kb SRAM with 8T unit cells. The sizing requirements for the 8T cell operated in subthreshold regime is explored as a function of static write margin. The subthreshold processor runs at 1 MHz with an energy consumption of 31 nJ/FFT. Subthreshold approach is seen to be the most energy efficient low power method of the three approaches.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132314830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Cleaning Up: Garbage-Free Reversible Circuits by Design Languages 清理:设计语言的无垃圾可逆电路
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.20
Michael Kirkedal Thomsen, Holger Bock Axelsen, R. Glück
{"title":"Cleaning Up: Garbage-Free Reversible Circuits by Design Languages","authors":"Michael Kirkedal Thomsen, Holger Bock Axelsen, R. Glück","doi":"10.1109/ISED.2012.20","DOIUrl":"https://doi.org/10.1109/ISED.2012.20","url":null,"abstract":"Reversible logic is a computational model that ensure that no values are discarded or duplicated. This gives the connection to Landauer's principle if and only if the underlying circuits are garbage-free. This paper shows how to describe and implement garbage-free reversible logic circuits in an easy and concise way. We use two domain-specific languages that are designed to describe reversible logic at different levels and garbage-free methods to translate between these. This approach relies heavily on programming language technology that is known and used for conventional functional languages. Though the languages ensure reversibility of the logic descriptions, they are not guaranteed to be garbage-free. It is still an important task for the designer to find the correct embeddings.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131247374","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries 将可逆电路映射到量子门库的最新进展
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.81
D. Michael Miller, Zahra Sasanian
{"title":"Recent Developments on Mapping Reversible Circuits to Quantum Gate Libraries","authors":"D. Michael Miller, Zahra Sasanian","doi":"10.1109/ISED.2012.81","DOIUrl":"https://doi.org/10.1109/ISED.2012.81","url":null,"abstract":"This paper reviews recent developments on mapping reversible circuits to libraries of elementary quantum gates. The emphasis is on optimization of both the initial reversible circuit and the resulting quantum circuit. At the quantum level, improved realizations of single mixed-polarity multiple-control Toffoli gates are presented as well as techniques for performing quantum gate optimizations across Toffoli gate boundaries. Experimental results show the effectiveness of the methods presented using circuits from the REVLIB benchmark suite.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116484035","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
System on Biochips: A New Design for Integration of Multiple DMFBs 生物芯片系统:一种集成多个dmfb的新设计
2012 International Symposium on Electronic System Design (ISED) Pub Date : 2012-12-19 DOI: 10.1109/ISED.2012.59
P. Roy, Moudud Sohid, Sudipta Chakraborty, H. Rahaman, P. Dasgupta
{"title":"System on Biochips: A New Design for Integration of Multiple DMFBs","authors":"P. Roy, Moudud Sohid, Sudipta Chakraborty, H. Rahaman, P. Dasgupta","doi":"10.1109/ISED.2012.59","DOIUrl":"https://doi.org/10.1109/ISED.2012.59","url":null,"abstract":"Digital microfluidic biochips have emerged in last decade as one of the major alternative platforms for employing conventional laboratory methods for biochemical and biomedical applications. On completion of the Bioassay protocols in DMFBs the detection is enabled at the scheduled optical detection sites within the chip area itself. Based on the detection results obtained from a series of tests in a single biochip - it may prompt to perform next sequence of tests in order to converge towards specific disease pattern and diagnosis. In this paper we have proposed a design of a centralized control system coupled with a droplet detection analyzer. The detection analyzer analyzes the combination of results for a series of test and feeds the result to a centralized controller that logically determines the next series of tests to be conducted on another biochip based on a intelligent database stored in the integrated memory of the system. The simulation is carried out on a series of tests for homogeneous samples in different biochips integrated together through the proposed central system controller and the detection results obtained from multiple DMFBs are displayed.","PeriodicalId":276803,"journal":{"name":"2012 International Symposium on Electronic System Design (ISED)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-12-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130370781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
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