Comparison of FFT/IFFT Designs Utilizing Different Low Power Techniques

Different techniques of power savings in CMOS circuits have been investigated through the years. This work compares the asynchronous approach, the superthreshold approach, and the subthreshold approach in a 128 point FFT processor. The subthreshold design, made in TSMC 65 nm technology, utilizes a 4 kb SRAM with 8T unit cells. The sizing requirements for the 8T cell operated in subthreshold regime is explored as a function of static write margin. The subthreshold processor runs at 1 MHz with an energy consumption of 31 nJ/FFT. Subthreshold approach is seen to be the most energy efficient low power method of the three approaches.