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A VLSI ATM Cell Processor for Broadband Network Subsystems 宽带网络子系统的VLSI ATM单元处理器
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759219
J. J. Hickey
{"title":"A VLSI ATM Cell Processor for Broadband Network Subsystems","authors":"J. J. Hickey","doi":"10.1109/HPCS.1992.759219","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759219","url":null,"abstract":"Broadband networks are designed for high-bandwidth time-sensitive traffic at speeds more than 10 times the speed of networks today. These speeds place extraordinary stress on the network sabsystems. Typically, subsystems designed for use in the broadband network make use of specialized hardware to provide necessary throughput. Such hardware is usually very restrictive in the types of traffic it can handle. New traffic types often requires changes in the hardware, which increases the cost and design time. To generalize the network interface hardware, we designed a special purpose experimental RISC processor in VLSI with an optimized instruction set, and on-board network communication interfaces. Network data are processed entirely on-chip under the control the the processing unit. The number of traffic types that can be handled is limited only by the time it takes to process the traffic type. This processor is intended for use in experimental broadband networks at speeds of 155-622 Mbps.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126978910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Intelligent Interworking Units, I/sup 2/Us a Proposal for the Lan/man/b-ISDN Environment 面向局域网/城域网/b-ISDN环境的智能互联单元I/sup 2/Us
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759243
M. Burak
{"title":"Intelligent Interworking Units, I/sup 2/Us a Proposal for the Lan/man/b-ISDN Environment","authors":"M. Burak","doi":"10.1109/HPCS.1992.759243","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759243","url":null,"abstract":"The paper proposes a new interworking concept called Intelligent Interworking Units (I/sup 2/Us). This concept is applied to the interconnection of IEEE 802.x LANs, IEEE 802.6 (DQDB) Metropolitan Area Networks (MANs) and ATM based B-ISDN. Between all the above mentioned network types Interworking Units (IWUs) are necessary to provide flexible communication capabilities. Today IWUs use a fixed layering scheme and are thus classified in bridges, routers or brouters. The I/sup 2/U concept enhances conventional IWUs to allow for a more sophisticated operation in a high-speed environment. I/sup 2/Us dynamically select the layers for interworking according to the received data type. This avoids encapsulation at the source and makes use of Layer 3 network functions only when needed. The proposed concepts relies on the special features of the DQDB MAN protocol which supports the concurrent use of different address types (16-, 48 and 60-bit) and the allocation of a set of addresses of each type to one node. The paper gives a short overview of the provision of connectionless services in the three mentioned network types, pointing out the differences concerning PDU formats and addressing schemes. The I/sup 2/Us concept for the interconnection of LANs via MANs and of MANs via the B-ISDN is subsequently described. The rationale for using the address translation mechanism only at the receiving IWU is also addressed. The I/sup 2/Us concept is part of the ongoing Enhanced Network- System (ENS) project at the GMD Berlin.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133229608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Atomic Lan 原子局域网
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759225
D. Cohen, G. Finn, R. Felderman, A. DeSchon
{"title":"The Atomic Lan","authors":"D. Cohen, G. Finn, R. Felderman, A. DeSchon","doi":"10.1109/HPCS.1992.759225","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759225","url":null,"abstract":"ATOMIC is an inexpensive O(gigabit) speed LAN built by USCASL it is based upon MOSAIC technology developed for fine-grain, message-passing, massively parallel computation. Each MOSAIC processor is capable of routing variable length packets, while providing added value through simultaneous computing and buffering. ATOMIC scales linearly, with a small interface cost. Each ATOMIC channel has a data carrying capacity of 640Mb/s. A prototype ATOMIC LAN has been constructed along with host interfaces and software that provides full TCP/IP compatibility. Using ATOMIC, 1,500 byte packets have been exchanged between hosts at a rate of more than WM. Other tests have demonstrated throughput of 2.6 million packets per second between two hosts. This paper describes the architecture and performance of ATOMIC.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131446756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Bergate: enhanced network system - system concept 贝尔盖特:强化网络系统-系统概念
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759118
A. Gavras, Xiangwen Xu
{"title":"Bergate: enhanced network system - system concept","authors":"A. Gavras, Xiangwen Xu","doi":"10.1109/HPCS.1992.759118","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759118","url":null,"abstract":"This paper describes a system architecture for a high performance system, which will provide high speed communication services over high speed networks available now or in the near future. Based on the experience of the design group form the BERGATE [1], [2], [3] project, we try in the design phase to consequently avoid any known system bottlenecks, such as conventional system buses, or heaveyweighted protocols. The system will provide support for existing protocols stacks, support for new applications that want to bypass protocol layers and support for the implementation of new lightweighted protocols.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127275729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Host Interface to the Dtm High Speed Network Dtm高速网络的主机接口
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759216
B. AhIgren
{"title":"A Host Interface to the Dtm High Speed Network","authors":"B. AhIgren","doi":"10.1109/HPCS.1992.759216","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759216","url":null,"abstract":"DTM dynamic synchronous transfer mode, is a new time division multiplexing technique for fiber networks currently being developed and implemented at the Royal Institute of Technology in Stockholm, Sweden. This paper describes the hardware and software aspects of the design of a SBus host interface to the DTM network for a Sun SPARCstation. The interface is based on a dual ported shared memory residing on the interface card and accessible over the SBus from the host CPU. The host operating system allocates message buffers directly in this memory. The interface has hardware support for segmenting and reassembling packets to and from the data units of the DTM. The software part of the interface manages the shared memory and the virtual circuits provided by the DTM network.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129032684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Parallel Protocol Implementations an Transputers - Experiences with OSI TP4, OSI CLNP, and XTP 并行协议实现和转译器——使用OSI TP4、OSI CLNP和XTP的经验
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759133
M. Zitterbart
{"title":"Parallel Protocol Implementations an Transputers - Experiences with OSI TP4, OSI CLNP, and XTP","authors":"M. Zitterbart","doi":"10.1109/HPCS.1992.759133","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759133","url":null,"abstract":"The demand for high performance communication subsystems has rapidly increased during the last few years. Emerging applications (e.g., multi-media applications) requiring high performance are one of the driving factors for this development. But still there is a performance gap of at least one order of magnitude between the bandwidth available on the network and the application requirements. This is based on the insufficient processing power inside communication nodes. They cannot serve networks with data rates in the range of Mbps to Gbps. To overcome this so-called transport bottleneck high performance architectures for communication subsystems have to be designed considering hardware and software structure as well as protocol design and service requirements. This paper presents an approach towards high performance communication platforms based on parallel protocol implementations on transputer networks. Thereby standard OSI protocols (TP4 and CLNP) as well as emerging lightweight protocols, such as XTP have been explored. The TP4 implementation is here presented more in detail and some experiences gained within this project are summarized.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115598166","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
On the Parallel Implementation of OSI Protocols 浅谈OSI协议的并行实现
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759135
Bernd Hofmann, Wolfgang Effelsberg, T. Held, Heinz König
{"title":"On the Parallel Implementation of OSI Protocols","authors":"Bernd Hofmann, Wolfgang Effelsberg, T. Held, Heinz König","doi":"10.1109/HPCS.1992.759135","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759135","url":null,"abstract":"In this paper we describe design considerations for the implementation of OSI protocols on parallel processors. We consider parallelism to be an appropriate technology for implementing protocols for high-speed networks. Parallelism can help to overcome the gap between fast fiber optics and slow protocol execution.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114489924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Fairness via Remote Management in a Dqdb Man Dqdb远程管理中的公平性
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759232
S. Covaci
{"title":"Fairness via Remote Management in a Dqdb Man","authors":"S. Covaci","doi":"10.1109/HPCS.1992.759232","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759232","url":null,"abstract":"The paper addresses the problem of fairness for the Queued Arbitrated in DQDB MANs. A solution to this problem in the form of a distributed management process called \"Fairness Management\" is proposed. The OSI Management and the DQDB specific management functionality we shortly over viewed and alternative management architectures based on standardized OSI concepts are subsequently specified. The functional description of the \"Fairness Management\" distributed process is given and the flexibility and potential of this solution are discussed. The paper also presents the ongoing implementation work along with a schedule of related simulation experiments within the framework of the BERKOM project activities.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123408586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Network Interface for a Multimedia Communication System 多媒体通信系统的网络接口
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759214
U. Rothlisberger
{"title":"A Network Interface for a Multimedia Communication System","authors":"U. Rothlisberger","doi":"10.1109/HPCS.1992.759214","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759214","url":null,"abstract":"In this paper the ETMUCS project with its novel network interface is introduced. The requirements of the communication system are elaborated, based on the functionality described. The implementation of the Interaction- Activity Model in hardware and software is briefly presented. The Network Interface Module is the core of the network interface. It bears some unusual features that can be exploited by the current node (switch) of the high speed fiber optic network.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129167076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analysis of the Nectar Communication Processor 蜜汁通信处理器的分析
IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems Pub Date : 1992-02-17 DOI: 10.1109/HPCS.1992.759112
P. Steenkiste
{"title":"Analysis of the Nectar Communication Processor","authors":"P. Steenkiste","doi":"10.1109/HPCS.1992.759112","DOIUrl":"https://doi.org/10.1109/HPCS.1992.759112","url":null,"abstract":"Nectar is a multicomputer built around a high-bandwidth crosspoint network. Nodes are connected to Nectar using network coprocessors (CABs) that do the protocol processing. The communication coprocessor is based on a general-purpose processor and runs a flexible runtime system. This allows us to offload application on the coprocessor and to experiment with different protocol implementations. An important network parameter for applications is the latency for short messages. In this paper we present an analysis of the CAB-CAB and host-host communication latency over Nectar for a number of communication protocols. We break up the latency and discuss how the components an influenced by the protocol implementation and node architecture.","PeriodicalId":274790,"journal":{"name":"IEEE Workshop on the Architecture and Implementation of High Performance Communication Subsystems","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1992-02-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114500972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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