2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)最新文献

Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units 基于规范的ARM VMSAv8-64内存管理单元测试程序生成

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.13

M. Chupilko, A. Kamkin, A. Kotsynyak, Alexander Protsenko, S. Smolov, A. Tatarnikov

{"title":"Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units","authors":"M. Chupilko, A. Kamkin, A. Kotsynyak, Alexander Protsenko, S. Smolov, A. Tatarnikov","doi":"10.1109/MTV.2015.13","DOIUrl":"https://doi.org/10.1109/MTV.2015.13","url":null,"abstract":"In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117281366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Performance of a SystemVerilog Sudoku Solver with VCS SystemVerilog数独求解器的性能研究

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.14

Jeremy Ridgeway

引用次数: 0

Harnessing Nanoscale Device Properties for Hardware Security 利用纳米级器件特性实现硬件安全

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.18

Bicky Shakya, Fahim Rahman, M. Tehranipoor, Domenic Forte

引用次数: 0

A Topological Approach to Hardware Bug Triage 硬件Bug分类的拓扑方法

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.10

Rico Angell, Ben Oztalay, A. DeOrio

{"title":"A Topological Approach to Hardware Bug Triage","authors":"Rico Angell, Ben Oztalay, A. DeOrio","doi":"10.1109/MTV.2015.10","DOIUrl":"https://doi.org/10.1109/MTV.2015.10","url":null,"abstract":"Verification is a critical bottleneck in the time to market of a new digital design. As complexity continues to increase, post-silicon validation shoulders an increasing share of the verification/validation effort. Post-silicon validation is burdened by large volumes of test failures, and is further complicated by root cause bugs that manifest in multiple test failures. At present, these failures are prioritized and assigned to validation engineers in an ad-hoc fashion. When multiple failures caused by the same root cause bug are debugged by multiple engineers at the same time, scarce, time-critical engineering resources are wasted. Our scalable bug triage technique begins with a database of test failures. It extracts defining features from the failure reports, using a novel, topology-aware approach based on graph partitioning. It then leverages unsupervised machine learning to extract the structure of the failures, identifying groups of failures that are likely to be the result of a common root cause. With our technique, related failures can be debugged as a group, rather than individually. Additionally, we propose a metric for measuring verification efficiency as a result of bug triage called Unique Debugging Instances (UDI). We evaluated our approach on the industrial-size OpenSPARC T2 design with a set of injected bugs, and found that our approach increased average verification efficiency by 243%, with a confidence interval of 99%.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132870212","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Characterizing Processors for Energy and Performance Management 用于能源和性能管理的处理器特性

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.22

Harshit Goyal, V. Agrawal

引用次数: 3

Automatic Bug Fixing 自动修复Bug

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.21

Daniel Hansson

引用次数: 3

Enhancing the Stress and Efficiency of RIS Tools Using Coverage Metrics 使用覆盖度量来增强RIS工具的压力和效率

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.19

John Hudson, Gunaranjan Kurucheti

引用次数: 1

Modeling and Analysis of Trusted Boot Processes Based on Actor Network Procedures 基于Actor网络过程的可信启动过程建模与分析

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.20

Mark Nelson, P. Seidel

引用次数: 1

Novel MC/DC Coverage Test Sets Generation Algorithm, and MC/DC Design Fault Detection Strength Insights 新型MC/DC覆盖测试集生成算法及MC/DC设计故障检测强度洞察

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.15

Mohamed A. Salem, K. Eder

引用次数: 1

Hybrid Post Silicon Validation Methodology for Layerscape SoCs involving Secure Boot: Boot (Secure & Non-secure) and Kernel Integration with Randomized Test 涉及安全引导的层级soc混合硅后验证方法:引导(安全和非安全)和随机测试的内核集成

2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV) Pub Date : 2015-12-01 DOI: 10.1109/MTV.2015.16

Amandeep Sharan, Ashish Gupta

{"title":"Hybrid Post Silicon Validation Methodology for Layerscape SoCs involving Secure Boot: Boot (Secure & Non-secure) and Kernel Integration with Randomized Test","authors":"Amandeep Sharan, Ashish Gupta","doi":"10.1109/MTV.2015.16","DOIUrl":"https://doi.org/10.1109/MTV.2015.16","url":null,"abstract":"Design advancements in semiconductor industry have resulted in shrinking schedules of time-to-market and improved quality assurance of the chips to be in perfect tandem with their specifications. Hence, Post-Silicon Validation, having a significant percentage in time-to-money, becomes one of the most highly leveraged steps in chip implementation. This also puts more pressure to reduce the validation cycle and automate extensively to speedup validation. Nowadays, companies are aiming for more complex designs in a shorter duration. So, as the SoC complexity keeps growing, we need real software applications, specialized and random tests to observe and check functionality, added with regression and electrical tests for checking chip specifications. For this, kernel boot is one of the best methodologies to run on the first silicon parts for a complete system test, which is followed by random tests & electrical validation. This paper presents a novel methodology for validation flow which facilitates kernel boot, both secure and non-secure, from various memory sources, integrating random test generation in every iteration. This flow also covers boot validation, electrical validation and complex scenarios like secure boot with deep sleep. It will cut down validation run time by 3-4 times, thus notably improving the performance which will lead to a major reduction in time to market. Other enhancements are in Customer Satisfaction Index (CSI) and Performance Quality Index (PQI) for boot and in shortening of electrical cycles.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122730784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1