Hybrid Post Silicon Validation Methodology for Layerscape SoCs involving Secure Boot: Boot (Secure & Non-secure) and Kernel Integration with Randomized Test

Design advancements in semiconductor industry have resulted in shrinking schedules of time-to-market and improved quality assurance of the chips to be in perfect tandem with their specifications. Hence, Post-Silicon Validation, having a significant percentage in time-to-money, becomes one of the most highly leveraged steps in chip implementation. This also puts more pressure to reduce the validation cycle and automate extensively to speedup validation. Nowadays, companies are aiming for more complex designs in a shorter duration. So, as the SoC complexity keeps growing, we need real software applications, specialized and random tests to observe and check functionality, added with regression and electrical tests for checking chip specifications. For this, kernel boot is one of the best methodologies to run on the first silicon parts for a complete system test, which is followed by random tests & electrical validation. This paper presents a novel methodology for validation flow which facilitates kernel boot, both secure and non-secure, from various memory sources, integrating random test generation in every iteration. This flow also covers boot validation, electrical validation and complex scenarios like secure boot with deep sleep. It will cut down validation run time by 3-4 times, thus notably improving the performance which will lead to a major reduction in time to market. Other enhancements are in Customer Satisfaction Index (CSI) and Performance Quality Index (PQI) for boot and in shortening of electrical cycles.