Int. J. High Speed Comput.最新文献_第3页

Simulation of Cycles in the IEH Graph IEH图中周期的模拟

Int. J. High Speed Comput. Pub Date : 1999-09-01 DOI: 10.1142/S0129053399000168

Jen-Chih Lin

引用次数: 4

Parallel Neural Learning for Control Problems on a Bus-Based Architecture 基于总线结构的并行神经学习控制问题

Int. J. High Speed Comput. Pub Date : 1999-09-01 DOI: 10.1142/S0129053399000120

T. Hong, Jyh-Jong Lee

引用次数: 0

A Comparative Study of Two Self Healing Protocols for ATM Networks ATM网络中两种自愈协议的比较研究

Int. J. High Speed Comput. Pub Date : 1999-09-01 DOI: 10.1142/S0129053399000119

Vikas Bajaj, A. Sarje

引用次数: 1

Comparisons of the Parallel Preconditioners on the Cray-T3E for Large Nonsymmetric Linear Systems 大型非对称线性系统Cray-T3E上并行预调节器的比较

Int. J. High Speed Comput. Pub Date : 1999-09-01 DOI: 10.1142/S0129053399000144

Sangback Ma

{"title":"Comparisons of the Parallel Preconditioners on the Cray-T3E for Large Nonsymmetric Linear Systems","authors":"Sangback Ma","doi":"10.1142/S0129053399000144","DOIUrl":"https://doi.org/10.1142/S0129053399000144","url":null,"abstract":"In this paper we consider five types of parallel preconditioners for solving large sparse nonsymmetric linear systems on the CRAY-T3E. They are ILU(0) in the wavefront ordering, ILU(0) in the multi-coloring ordering, SSOR in the wavefront ordering, the SPAI(SParse Approximate Inverse) preconditioner, and finally Multi-color Block SOR preconditioner. The ILU(0) is known to be robust and the wavefront ordering naturally exploits the parallelism but has a limited speedup due to the nonuniform lengths of the wavefronts. Multi-coloring is an efficient way of introducing the parallelism of order(N), where N is the order of the matrix but the convergence rate often deteriorates. The SPAI type preconditioner is inherently parallel and is gaining popularity. Finally, for the 5-point Laplacian matrix SOR method is known to have a nondeteriorating rate of convergence when the multi-coloring order is adopted. Also, Block SOR is expected to incur less communication overheads in a message-passing machine. Hence, Multi-Color Block SOR method is expected to have a good performance. Experiments were conducted for the Finite Difference discretizations of two problems with various meshsizes varying up to 1024×1024. MPI library was used for interprocess communications. The results show that ILU(0) in the multi-coloring ordering gives the best performance.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"173 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120881089","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Simulation Study of Combining Load Value and Address Predictors 负载值与地址预测器相结合的仿真研究

Int. J. High Speed Comput. Pub Date : 1999-09-01 DOI: 10.1142/S0129053399000156

Toshinori Sato

引用次数: 4

Constant Propagation in a Hierarchical Intermediate Program Representation 分层中间程序表示中的常数传播

Int. J. High Speed Comput. Pub Date : 1999-06-01 DOI: 10.1142/S0129053399000089

M. Giordano, M. Furnari, Renata Napolitano, Antonio Spagnolo

{"title":"Constant Propagation in a Hierarchical Intermediate Program Representation","authors":"M. Giordano, M. Furnari, Renata Napolitano, Antonio Spagnolo","doi":"10.1142/S0129053399000089","DOIUrl":"https://doi.org/10.1142/S0129053399000089","url":null,"abstract":"A crucial problem in parallelizing compiler design is the choice of a suitable Intermediate Representation (IR) to make parallelism detection and extraction easy and possible. Dependence graphs have long been recognized as useful tools for this aim. Several versions were proposed [1,4,6,20], which encapsulate relations of data dependence, control dependence or both. They were also used in conventional optimizations, but always coupled with the traditional Control Flow Graph (CFG). However, it would be preferable to apply both conventional and parallelizing optimizations to the same IR. Recently, some attempts were made to use dependence graphs as a unifying framework on which all types of optimization [4] are applied. This is one of the aims of our work in this research area. We started working on the well known Hierarchical Task Graph (HTG) of Polychronopoulos and Girkar [6,7,8]. The HTG, by definition, is an acyclic and then a reducible graph. In fact it is built from a CFG arranged hierarchically around loops with all loop back edges removed. This CFG is then enriched with control and data dependence information (edges). Our proposal is an extension of the HTG, named Extended Hierarchical Task Graph (EHTG), that is a HTG where data dependence edges are annotated with a boolean branch path expression indicating the CFG paths through which the data dependences are established. We developed two algorithms of constant propagation (used for dead code elimination) running directly on our EHTG without using the traditional CFG. The two algorithms can be applied only to sequential programs whose parallelism is represented by the HTG structure. They are not suited to perform constant propagation on explicitly parallel programs [12]. Complexity and correctness of the algorithms are analyzed and we also prove that one of them has the same complexity and finds the same class of constants as the well known Wegman & Zadeck constant propagation algorithm [20], that uses a hybrid sparse representation.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126499426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Shared Memory Multiprocessor System for the Recognition of solid Objects 面向实体物体识别的共享内存多处理器系统

Int. J. High Speed Comput. Pub Date : 1999-06-01 DOI: 10.1142/S0129053399000077

M. Yaqub, Q. Shaikh, S. Ahmad

引用次数: 0

Diagonal-Implicitly Iterated Runge-Kutta Methods on Distributed Memory Machines 分布式存储机器上的对角隐式迭代龙格-库塔方法

Int. J. High Speed Comput. Pub Date : 1999-06-01 DOI: 10.1142/S0129053399000090

T. Rauber, G. Rünger

引用次数: 10

Vector and Parallel Implementations for the FDTD Analysis of Millimeter Wave Planar Antennas 毫米波平面天线时域有限差分分析的矢量与并行实现

Int. J. High Speed Comput. Pub Date : 1999-06-01 DOI: 10.1142/S0129053399000107

H. Hoteit, R. Sauleau, B. Philippe, P. Coquet, J. Daniel

引用次数: 29

Dynamic Load Assignment of Real-Time Tasks in Distributed Memory Multiprocessors 分布式内存多处理器实时任务的动态负载分配

Int. J. High Speed Comput. Pub Date : 1999-03-01 DOI: 10.1142/S0129053399000053

Yacine Atif

{"title":"Dynamic Load Assignment of Real-Time Tasks in Distributed Memory Multiprocessors","authors":"Yacine Atif","doi":"10.1142/S0129053399000053","DOIUrl":"https://doi.org/10.1142/S0129053399000053","url":null,"abstract":"In this paper, we consider a scalable distributed-memory architecture for which we propose a problem representation that assigns real-time tasks on the processing units of the architecture to maximize deadline compliance rate. Based on the selected problem representation, we derive an algorithm that dynamically schedules real-time tasks on the processors of the distributed architecture. The algorithm uses a formula to generate the adequate scheduling time so that deadline loss due to scheduling overhead is minimized while deadline compliance rate is being maximized. The technique we propose proved to be correct in the sense that the delivered solutions are not obsolete, i.e., the assigned tasks to working processors are guaranteed to meet their deadlines once executed. The correctness criterion is obtained based on our technique to control the scheduling time. To evaluate the performance of the algorithms that we propose, we provide a number of experiments through a simulation study. We also propose an implementation of our algorithms in the context of scheduling real-time transactions on an Intel-Paragon distributed-memory multiprocessor. The results of the conducted experiments show interesting performance trade-offs among the candidate algorithms.","PeriodicalId":270006,"journal":{"name":"Int. J. High Speed Comput.","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121843513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0