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2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits最新文献

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Advanced scan chain failure analysis using laser modulation mapping and continuous wave probing 先进的扫描链失效分析使用激光调制映射和连续波探测
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306326
S. Kasapi, W. Lo, J. Liao, B. Cory, H. Marks
{"title":"Advanced scan chain failure analysis using laser modulation mapping and continuous wave probing","authors":"S. Kasapi, W. Lo, J. Liao, B. Cory, H. Marks","doi":"10.1109/IPFA.2012.6306326","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306326","url":null,"abstract":"Scan chain failures are a significant fraction of yield loss. The complexity of modern design-for-test (DFT) implementation techniques and more subtle failure mechanisms of sub-40nm technologies make defect identification more challenging. Software chain diagnosis and a variety of EFA techniques have been deployed to improve scan chain failure isolation. However, we have found in practice that each of these techniques has significant limitations. In earlier papers we presented a new image-based laser technique (Modulation Mapping) to identify the first failing flop in the broken scan chain of stuck-at failures. Here we present three case studies of scan chains with more subtle resistive failure mechanisms, including transition, bridge, and slow-to-rise/fall failures, using a combination of modulation mapping (MM) and continuous-wave (CW) laser probing.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124292072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Failure Analysis of damaged dielectric on resistor and capacitor with EMMI and IR-OBIRCH EMMI和IR-OBIRCH对电阻器和电容器上损坏介质的失效分析
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306276
Li Tian, Miao Wu, Diwei Fan, Chunlei Wu, Gaojie Wen, Dong Wang
{"title":"Failure Analysis of damaged dielectric on resistor and capacitor with EMMI and IR-OBIRCH","authors":"Li Tian, Miao Wu, Diwei Fan, Chunlei Wu, Gaojie Wen, Dong Wang","doi":"10.1109/IPFA.2012.6306276","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306276","url":null,"abstract":"With scaling down of semiconductor devices, gate oxide degradation has been a reliability problem. So, emission microscope was developed to be applied in damaged gate oxide analysis in recent 20 years. We usually occurred some fail capacitor and resistor cases in FA (Failure Analysis). But in FA field no any paper summarized analysis of damaged capacitor and resistor with EMMI (Emission Microscope) and IR-OBIRCH (Infrared Optical Beam Induced Resistor Change) so far. So, it was very necessary to study EMMI & IR-OBIRCH characteristic of damaged dielectric on capacitor or resistor. In this paper, according our analysis experience and study structure of device there was similar insulation structure for gate oxide in MOS and dielectric in capacitor & resistor. Emission mechanism of damaged dielectric on capacitor and resistor was described, meanwhile we pointed out CCD could detect luminescence emitted by damaged dielectric layer. Three real cases were shared with abnormal emission spot on capacitor or resistor and in two of them we captured abnormal hotspot at abnormal emission spot location with IR-OBIRCH successfully. Finally we concluded one rule: once emission spot or hotspot was captured on capacitor or resistor with EMMI or IR-OBIRCH analysis, there must be damaged dielectric on this capacitor or resistor.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124893224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Improving yield learning by rapid electrical fault inspection and localization 通过快速电气故障检测和定位提高良率学习
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306319
Beomjun Kim, Jongtaek Hong, Yongwoon Han, I. Kapilevich, J. Block, T. Lundquist, Myung Hwan Kim
{"title":"Improving yield learning by rapid electrical fault inspection and localization","authors":"Beomjun Kim, Jongtaek Hong, Yongwoon Han, I. Kapilevich, J. Block, T. Lundquist, Myung Hwan Kim","doi":"10.1109/IPFA.2012.6306319","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306319","url":null,"abstract":"From wafer sort to yield learning is a long, complex process. Even worst because when scan chains fail, wafer sort adds negligible value. To address this gap a fast, reliable and accurate localization technology for scan chain fails that enable rapid translation of these into yield learning is presented.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122395303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Anomalous single bit retention induced by asymmetric STI-corner-thinning for floating gate Flash memories 浮动门闪存中不对称sti角变薄引起的异常单比特保留
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306323
Ming-Yi Lee, Wei-Hao Hsiao, Ru-Ping Chen, Li-Kuang Kuo, Sheng-Qian Dai, Rong-Cyuan Ting, Chih-Lin Chen, Da-Gang Chu, Chih-Yuan Lu
{"title":"Anomalous single bit retention induced by asymmetric STI-corner-thinning for floating gate Flash memories","authors":"Ming-Yi Lee, Wei-Hao Hsiao, Ru-Ping Chen, Li-Kuang Kuo, Sheng-Qian Dai, Rong-Cyuan Ting, Chih-Lin Chen, Da-Gang Chu, Chih-Yuan Lu","doi":"10.1109/IPFA.2012.6306323","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306323","url":null,"abstract":"Data retention is a major issue that significantly affects the reliability of Flash memories. In this work, the method of P-Well-Inside stress with a low electric field was used to effectively detect the stress induced leakage current that caused single bit retention due to non-optimized process in NOR-type floating-gate Flash memories. Based on the electrical and physical failure analysis, the asymmetric corner thinning of Shallow-Trench-Isolation induced by the asymmetric cell implantation was identified as the origin of the retention failure. In consequence, the proposed method of P-Well-Inside stress provides a new and fast evaluation for data retention and process optimization.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122613402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
New and novel failure analysis technique of COL package device with WBC non conductive epoxy and The failure mechanisms of the electrical shorting of the die back to the lead WBC不导电环氧树脂COL封装器件失效分析新技术及模具回引线电短路失效机理
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306280
Z. J. Lau, H. S. Foo, Y. M. Yusof, Y. S. Lee, Lik Ting Law
{"title":"New and novel failure analysis technique of COL package device with WBC non conductive epoxy and The failure mechanisms of the electrical shorting of the die back to the lead","authors":"Z. J. Lau, H. S. Foo, Y. M. Yusof, Y. S. Lee, Lik Ting Law","doi":"10.1109/IPFA.2012.6306280","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306280","url":null,"abstract":"Chip on Leads or COL is a package without the Die Flag or Die Attach Pad (DAP), where the Die is bonded directly on the leads using non-conductive epoxy as the electric isolation material between the die back and the leads. Problem arises when the electrical isolation between the die back and leads has failed. Identifying the electrical short path between the die back and the leads is a challenge for failure analysis of COL package. One need to understand the device bill of material (BOM), bonding diagram and package structure before this COL die back to lead short failure mode can be confirmed by a method of combination of die isolation from the package and micro-probing. Thermal-Induced-Voltage-Alteration (TIVA) was then used to locate the physical bridging between die back and lead. This paper entails the challenge in identifying the electrical shorting path on bench, the TIVA and progressive FIB technique. Failure mechanisms are also discussed.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122655995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure analysis of latent damage in low temperature poly-silicon TFT for OLED applications OLED低温多晶硅TFT潜在损伤失效分析
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306314
Dong-Sun Kim, Chun-Bae Lim, Seung-Won Jung, Du-Seok Oh, Hyung-Tae Kim, Wonjoon Ho, J. Jung, J. Shim, Tae-Young Kim, K. Suh
{"title":"Failure analysis of latent damage in low temperature poly-silicon TFT for OLED applications","authors":"Dong-Sun Kim, Chun-Bae Lim, Seung-Won Jung, Du-Seok Oh, Hyung-Tae Kim, Wonjoon Ho, J. Jung, J. Shim, Tae-Young Kim, K. Suh","doi":"10.1109/IPFA.2012.6306314","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306314","url":null,"abstract":"Optical microscope and FIB were widely used to find out defect locations in display panels. But failure analysis of LTPS TFTs is getting more difficult to detect the locations than that of (a-Si:H) TFTs. We adopted FIB and EMMI tool and found the leakage path on some special function failure such as line defect in display panel. Analysis results would help to find out defects and improve the yield by introducing right analysis method of FIB/EMMI tools in display panels.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114164370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Characterization of Si nanowires-based piezoresistive pressure sensor by dynamic cycling test 基于硅纳米线的压阻式压力传感器动态循环特性研究
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306318
Liang Lou, Hongkang Yan, Cairan He, W. Park, D. Kwong, Chengkuo Lee
{"title":"Characterization of Si nanowires-based piezoresistive pressure sensor by dynamic cycling test","authors":"Liang Lou, Hongkang Yan, Cairan He, W. Park, D. Kwong, Chengkuo Lee","doi":"10.1109/IPFA.2012.6306318","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306318","url":null,"abstract":"A novel pressure sensor using piezoresistive silicon nanowires (SiNWs) embedded in the suspended multi-layered diaphragm was investigated by a probe-based dynamic cycling test. Even under compressive strain of 1.5% after 3.6×105 cycles, there is no observed drift and degradation in sensor characteristics.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129570386","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Lock-in IR-OBIRCH assisted with current detection probe head extend its application to high voltage high current failure analysis 锁定IR-OBIRCH辅助电流检测探头将其应用范围扩展到高压大电流故障分析
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306245
Chunlei Wu, Li Tian, Miao Wu, Diwei Fan
{"title":"Lock-in IR-OBIRCH assisted with current detection probe head extend its application to high voltage high current failure analysis","authors":"Chunlei Wu, Li Tian, Miao Wu, Diwei Fan","doi":"10.1109/IPFA.2012.6306245","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306245","url":null,"abstract":"Lock-in IR-OBIRCH analysis is very effective for defect localization in failure analysis. However, there are some cases that only have failures under high voltage and high current condition, which limits the application of Lock-in IR-OBIRCH as it only supply maximal 25V voltage and 100mA current. Current Detection Probe Head extend its capability that can supply maximal 250V voltage and 6.3A current, which supply a good solution about defect localization for high voltage and high current failure mode.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128588476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Local current measurements for avalanche breakdown in Silicon p-n junctions 硅p-n结雪崩击穿的局部电流测量
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306254
Y. Ding, D. Poenar, D. Isakov
{"title":"Local current measurements for avalanche breakdown in Silicon p-n junctions","authors":"Y. Ding, D. Poenar, D. Isakov","doi":"10.1109/IPFA.2012.6306254","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306254","url":null,"abstract":"Application of Photon Emission Microscopy (PEM) in semiconductor characterization often shows a linear dependence between emission intensity and biasing current. However, inconclusive understanding of photon emission phenomena in Silicon stopped the research community form applying PEM for local current estimation. In this paper we show for the first time that the linear relationship is valid for avalanche breakdown in the range of currents across five orders of magnitude. And we conclude that the observed relationship is independent of non-radiative effects. Using the observed photon emission pattern we perform a detailed analysis of the influence of the junction geometry and doping topology on the breakdown phenomenon. We also for the first time estimate the local I-V curves in the junction and demonstrate the complexity of the breakdown phenomenon. Our results also demonstrate a poor applicability of global I-V curve measurements for calibration of existing TCAD models.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130304666","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reliability analysis of CrSi Thin Film Resistors CrSi薄膜电阻的可靠性分析
2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits Pub Date : 2012-07-02 DOI: 10.1109/IPFA.2012.6306282
C. W. Khor, C. Leung, O. Le Néel
{"title":"Reliability analysis of CrSi Thin Film Resistors","authors":"C. W. Khor, C. Leung, O. Le Néel","doi":"10.1109/IPFA.2012.6306282","DOIUrl":"https://doi.org/10.1109/IPFA.2012.6306282","url":null,"abstract":"CrSi Thin Film Resistor (TFR) is mainly used due to its high precision of less than 1% standard deviation and low thermal coefficient of resistance (TCR) with zero drift with temperature. Reliability characterization is studied on CrSi Thin Film Resistors (TFRs) to understand the reliability behaviour of CrSi Thin Film Resistors. Current sweep is performed on TFRs structures to determine current density threshold before catastrophic resistance degradation. Constant Current stress is performed at several currents to characterize the resistance change of TFRs with current. 2 models are proposed for lifetime stability prediction of TFRs.","PeriodicalId":267457,"journal":{"name":"2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2012-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129175892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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