2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)最新文献_第10页

An easy guide for inverter design for residential smart building applications 住宅智能建筑应用逆变器设计的简单指南

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261577

A. Valderrábano‐González, J. Rosas-Caro, F. Beltrán-Carbajal, R. Tapia-Olvera, H. Gabbar, A. Sharaf

引用次数: 2

A high step-up DC-DC converter with MPPT for PV application 一个高升压DC-DC转换器与MPPT的光伏应用

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261610

M. del Rosario Rivera-Espinosa, Alfredo Y. Alejandre-López, Jesus E. Pedraza-Barrón, P. García-Vite, Héctor R. Robles-Campos

引用次数: 3

Classification of partial discharge in pin type insulators using fingerprints and neural networks 引脚型绝缘子局部放电的指纹和神经网络分类

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261653

M. Quizhpi-Cuesta, F. Gómez-Juca, W. Orozco-Tupacyupanqui, F. Quizhpi-Palomeque

{"title":"Classification of partial discharge in pin type insulators using fingerprints and neural networks","authors":"M. Quizhpi-Cuesta, F. Gómez-Juca, W. Orozco-Tupacyupanqui, F. Quizhpi-Palomeque","doi":"10.1109/ROPEC.2017.8261653","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261653","url":null,"abstract":"The classification of partial discharge (PD) or partial breakdown (PB) is an important issue that helps to identify the cause of this electrical phenomenon in pin type insulators. In this work, a PD classification method based on neural networks (NN) is proposed. This sorting technique consists of three parts. First, the detection and measurement of partial discharge are achieved by using a digital finite impulse response (FIR) filter, whose main objective is to obtain electrical charges with significant characteristics of the PB. The second part of the process deals with the classification of partial discharge. A statistical analysis is implemented to obtain PD patterns or fingerprints which are classified by a neural network. Finally, the third part of the proposed method focuses on interpreting the information obtained from the NN and determining the PD current in the pin isolator. The results show that this proposed technique of analysis and detection of partial discharge in pin type isolators is successful in optimizing the time of analysis and classification of PB.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127913709","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Multi-level inverter connected to the grid with harmonic mitigation for photovoltaic power injection 多级逆变器并网谐波缓解光伏发电注入

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261662

Francisco Ramón Urquijo Ramos, J. Ramírez, J. Jiménez, L. Hernández

引用次数: 2

Reducing energy consumption in an industrial process by using model predictive control 利用模型预测控制降低工业过程中的能耗

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261618

Luis Caiza, Albert Rosich-Oliva, C. Ocampo‐Martinez, D. Benítez

引用次数: 4

Using input-output correlations and a modified slide attack to compromise IEC 62055-41 使用输入输出相关性和修改的滑动攻击来破坏IEC 62055-41

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261692

Reagan Mbitiru, T. Ustun

{"title":"Using input-output correlations and a modified slide attack to compromise IEC 62055-41","authors":"Reagan Mbitiru, T. Ustun","doi":"10.1109/ROPEC.2017.8261692","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261692","url":null,"abstract":"Developed initially for pre-paid electricity meters in South Africa, the IEC 662055-41 standard is now the world's most ubiquitous open pre-paid metering standard. The standard is used in 35 million meters operated in 400 utilities in 30 countries. It now serves more users in Asia than in Africa. The standard uses 16 cycles of a block-cipher-like substitution and permutation process to both generate 20 digit tokens (through an encryption process) and to decode 20 digit tokens and determine the number of kWhs procured (through a decryption process), in conjunction with a 64 bit decoder key generated using the Data Encryption standard (DES). Despite its popularity, there is little work on the cryptology aspects of this standard. This paper discusses two types of cryptanalysis techniques used to attack this pre-paid metering standard. The first is a statistical analysis of the encrypted and decrypted inputs and outputs to determine if any correlation between them exists. The second is the use of slide attacks, a technique traditionally used for attacking block ciphers that use the same or ‘weak’ round keys for each encryption/decryption cycle. Using this second cryptanalysis attack, it is shown that 16 of the 64 bits of the decoder key can be exposed, an aspect not intended by its designers. Further combination with other techniques may be used to compromise the entire key.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132880972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Experimental determination of the nonlinear model for a proportional hydraulic valve 比例液压阀非线性模型的实验确定

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261602

Jose F. Tenesaca, Marco Carpio, R. Saltarén, G. Portilla

引用次数: 1

Real-time Mexican Sign Language recognition 实时墨西哥手语识别

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261606

Candy Obdulia Sosa-Jimenez, H. Rios-Figueroa, E. Rechy-Ramirez, A. Marín-Hernández, Ana Luisa Solís González-Cosío

引用次数: 9

Low noise rail-to-rail amplifier runs fast at ultra low currents and targets energy harvesting 低噪声轨对轨放大器在超低电流下快速运行，目标是能量收集

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261575

Ali Far

{"title":"Low noise rail-to-rail amplifier runs fast at ultra low currents and targets energy harvesting","authors":"Ali Far","doi":"10.1109/ROPEC.2017.8261575","DOIUrl":"https://doi.org/10.1109/ROPEC.2017.8261575","url":null,"abstract":"An input-output rail-to-rail buffer amplifier is presented that is low noise, fast, and operates at ultra low currents. The amplifier targets energy harvesting applications that require low cost, high volume, and rugged manufacturing by avoiding use of non-standard device configurations or special processes. The main contributions of this work are: (1) The method of lowering voltage output noise by narrow-banding an amplifier, while introducing a time dependent bias current boost that is triggered by large differential input signals. Narrowbanding an amplifier to reduce its output noise, slows its dynamic response, and this method aims to restore and boost both the amplifier's slew rate and settling time. (2) Amplifier can operate at low VDD of about VGS+2VDS, while running in subthreshold, based in standard 0.18u digital CMOS. (3) PMOSFETs are utilized as inputs, compensation capacitors, and bias resistors in both the amplifier and the boost stages, which helps optimize for yield and lower noise. More importantly, the dynamic response of both the main amplifier and the boost stage being substantially dependent on PMOSFET device parameters, facilitates a smoother dynamic response in and out of boost, over process and operating variations. Based on montecarlo (MC) and worst case (WC) simulations, the following specifications are achievable: voltage output noise (VO<inf>nOiSe</inf>) of 10 uv/Hz⁁1/2 at 1KHz, supply current (Idd) ∼ 500 nA; V<inf>dd</inf> minimum ∼0.6V; rail-to-rail voltage input (V<inf>IN</inf>) range and output voltage (V<inf>OUT</inf>) range of ∼ +/− 25mv from the rails; output resistor load (R<inf>l</inf>) ∼2k Ohms; output capacitor load (C<inf>l</inf>) ∼1nF; slew-rate (SR) −/+ ∼ 4/2.5 v/us; settling time (t<inf>S</inf>) ∼ 5us to 1%; power supply rejection ratio (PSRR) −/+ ∼ 80dB/85dB, common mode rejection ration (CMRR) ∼ 125dB, unity gain bandwidth (f<inf>r</inf>) ∼ 20KHz with phase margin (PM) ∼ 75 degrees; open loop gain (G) ∼ 85dB; preliminary area estimate of ∼ 180 um per side.","PeriodicalId":260469,"journal":{"name":"2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126799745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

Mobility extraction for 24-nm-channel length n-MOS using the RFCV technique: Effect of the fabrication process 利用RFCV技术提取24nm通道长度n-MOS的迁移率:制备工艺的影响

2017 IEEE International Autumn Meeting on Power, Electronics and Computing (ROPEC) Pub Date : 2017-11-01 DOI: 10.1109/ROPEC.2017.8261677

L. Trojman, Diego R. Benalcázar, L. Prócel, Guillaume Jobard

引用次数: 0