ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis最新文献

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X-Ray Computed Tomography: A Potentially Destructive “Non-Destructive Evaluation” Technique x射线计算机断层扫描:一种潜在破坏性的“非破坏性评估”技术
Ryan Ross, Gil Garteiz, S. Zajac
{"title":"X-Ray Computed Tomography: A Potentially Destructive “Non-Destructive Evaluation” Technique","authors":"Ryan Ross, Gil Garteiz, S. Zajac","doi":"10.31399/asm.cp.istfa2019p0519","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0519","url":null,"abstract":"\u0000 Characterization of Computed Tomography X-Ray ionizing dose will be presented along with a methodology to protect space bound flight hardware from exceeding total ionizing dose (TID) budget prior to mission completion.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128574916","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NanoProbing on 7 nm FinFET Devices in an SRAM Array: Challenges and Solutions SRAM阵列中7nm FinFET器件的纳米探测:挑战与解决方案
Anqi Qiu, W. Lowe, Mridul Arora
{"title":"NanoProbing on 7 nm FinFET Devices in an SRAM Array: Challenges and Solutions","authors":"Anqi Qiu, W. Lowe, Mridul Arora","doi":"10.31399/asm.cp.istfa2019p0329","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0329","url":null,"abstract":"\u0000 Nanoprobing systems have evolved to meet the challenges from recent innovations in the semiconductor manufacturing process. This is demonstrated through an exhibition of standard SRAM measurements on TSMC 7 nm FinFET technology. SEM based nanoprober is shown to meet or exceed the requirements for measuring 7nm technology and beyond. This paper discusses in detail of the best-known methods for nanoprobing on 7nm technology.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"38 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116541271","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Transistor Level Reliability Assessment of Gate Oxide Defects by BTI Stress Nanoprobing 基于BTI应力纳米探针的栅极氧化物缺陷晶体管级可靠性评估
D. Albert, Z. Song, M. Tenney, Patricia A. Mcginnis, Johns Oarethu
{"title":"Transistor Level Reliability Assessment of Gate Oxide Defects by BTI Stress Nanoprobing","authors":"D. Albert, Z. Song, M. Tenney, Patricia A. Mcginnis, Johns Oarethu","doi":"10.31399/asm.cp.istfa2019p0346","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0346","url":null,"abstract":"\u0000 This paper presents Electrical Failure Analysis (EFA) and Physical Failure Analysis (PFA) on a random time zero (t0) gate oxide defect within an IBM processor manufactured with a 14nm SOI (Silicon On Insulator) FinFET technology. The natures of the Functional Fail, the gate oxide defect, and the transistor characteristics are included.\u0000 The impact of this gate oxide defect to product yield and performance, plus the extent to which it extends across the product chip, which includes passing circuits, is covered. Since chips, which may contain this defect, could be present within the entire product lifecycle, the reliability aspects of the defect at the transistor level were investigated.\u0000 Among the various reliability stresses available for transistors, Constant Voltage Stress (CVS) Bias Temperature Instability (BTI) was chosen. CVS BTI stressing was able to be performed on both the NFETs and PFETs within the Inverter of the failing circuit, plus other identical reference circuits.\u0000 The BTI stress nanoprobing is covered. This includes an overview of BTI stressing, confirming the nanoprobing system and electrical stress/test programs are adequate for BTI stressing, BTI stress methodologies for Inverters, plus the BTI stress results.\u0000 The transistor level BTI stress results are discussed and compared to other published BTI literature. Finally, the reliability aspects of this gate oxide defect are discussed.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115732148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
2D carrier Density Mapping Using SNDM-dC/dV and dC/dz of SiC Power MOSFET 基于SiC功率MOSFET SNDM-dC/dV和dC/dz的二维载流子密度映射
Jing-jiang Yu, T. Yamaoka, T. Aiso, K. Watanabe, Y. Shikakura, S. Kudo, K. Tamura, K. Mizuguchi
{"title":"2D carrier Density Mapping Using SNDM-dC/dV and dC/dz of SiC Power MOSFET","authors":"Jing-jiang Yu, T. Yamaoka, T. Aiso, K. Watanabe, Y. Shikakura, S. Kudo, K. Tamura, K. Mizuguchi","doi":"10.31399/asm.cp.istfa2019p0494","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0494","url":null,"abstract":"\u0000 Scanning nonlinear dielectric microscopy is continuously developed as an AFM-derived method for 2D dopant profiling of semiconductor devices. In this paper, the authors apply 2D carrier density mapping to Si and SiC and succeed a high resolution observation of the SiC planar power MOSFET. Furthermore, they develop software that combines dC/dV and dC/dz images and expresses both density and polarity in a single distribution image. The discussion provides the details of AFM experiments that were conducted using a Hitachi environmental control AFM5300E system. The results indicated that the carrier density decreases in the boundary region between n plus source and p body. The authors conclude that although the resolutions of dC/dV and dC/dz are estimated to be 20 nm or less and 30 nm or less, respectively, there is a possibility that the resolution can be further improved by using a sharpened probe.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132155842","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Failure Analysis on Inter Polysilicon Oxide Reliability Issues of 40nm Automotive NVM Device 40nm汽车NVM器件内部多晶硅氧化物可靠性问题失效分析
P. K. Tan, R. Fransiscus, Y. L. Pan, H. Thoungh, S. L. Ting, Y. Z. Zhao, T. L. Wee, Hao Tan, S. Neo, C. Q. Chen
{"title":"Failure Analysis on Inter Polysilicon Oxide Reliability Issues of 40nm Automotive NVM Device","authors":"P. K. Tan, R. Fransiscus, Y. L. Pan, H. Thoungh, S. L. Ting, Y. Z. Zhao, T. L. Wee, Hao Tan, S. Neo, C. Q. Chen","doi":"10.31399/asm.cp.istfa2019p0340","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0340","url":null,"abstract":"\u0000 Reliability tests, such as Time-Dependent Dielectric Breakdown (TDDB), High-Temperature Operating Life (HTOL), Hot Carrier Injection (HCI), etc., is required for the lifetime prediction of an integrated circuit (IC) product. Those reliability tests are more stringent and complex especially for automotive Complementary Metal–Oxide–Semiconductor (CMOS) devices, this because it involves human lives and safety. In foundries failure analysis (FA), Transmission Electron Microscopy (TEM) analysis often required in order to provide insights into the defect mechanisms and the root cause of the reliability tests. In this paper, application of high resolution Nano-probing Electron Beam Absorbance Current (EBAC), Nano-probing active passive voltage contrast (APVC), and TEM with Energy Dispersive X-Ray Spectroscopy (EDX) to identify the failing root cause of Inter- Poly Oxide (IPO) TDDB failure on an automotive grade Non- Volatile Memory (NVM) device was investigated. We have successfully demonstrated that TEM analysis after Nanoprobing EBAC/APVC fault isolation is an effective technique to reveal the failure root cause of IPO breakdown after reliability stresses.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130456732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
The Investigation of Oven Contamination and Corresponding Methodology 烘箱污染的调查及相应的方法
W. Hsieh, Henry Lin, Vincent Chen, Jun Liu, Irene Ou, Y. Lou
{"title":"The Investigation of Oven Contamination and Corresponding Methodology","authors":"W. Hsieh, Henry Lin, Vincent Chen, Jun Liu, Irene Ou, Y. Lou","doi":"10.31399/ASM.CP.ISTFA2019P0426","DOIUrl":"https://doi.org/10.31399/ASM.CP.ISTFA2019P0426","url":null,"abstract":"\u0000 Contamination and particle reduction are critical to semiconductor process control. Lots of failure analysis had been focused on finding the root cause of the particle and contamination. The particle and contamination effect were also easily found in circuit probing (CP) process, and therefore induced yield loss and wafer scrap. In the first part of this paper, an oven contamination case was studied. The second part of this paper focus on oven contamination monitoring.\u0000 In the beginning, a die flying failure was papered at the stage of blue tape and die sawing. This event clearly indicated bad adhesion between die and plastic tape. This bad adhesion was suspected to be a particle/contamination layer formed on bad die surface. Three failure analysis (FA) approaches were performed to find out the root cause. The SEM/EDS result identified the main elements of big particle, but that is insufficient to identify the root cause. The OM/FTIR, however, showed the contamination may be related to polydimethylsiloxane (PDMS). The last failure analysis was the time of fly Secondary Ion Mass Spectrometer (TOF-SIMS), the result confirmed that there was a thin PDMS layer formed on the contaminated bad die surface. The high temperature CP process induced PDMS is believed to be the contamination root cause. In order to prevent the oven contamination event, a methodology based on contact angle and wettability of Si matrix sample was set up for regular monitor in oven operation. The details of contact angle test (CAT) sample preparation, measurement and analysis results were also discussed in this paper.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126031976","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Targeted Silicon Ultra-Thinning by Contour Milling for Advanced Fault Isolation 轮廓铣削定向硅超薄技术用于高级故障隔离
W. S. Teo
{"title":"Targeted Silicon Ultra-Thinning by Contour Milling for Advanced Fault Isolation","authors":"W. S. Teo","doi":"10.31399/asm.cp.istfa2019p0472","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0472","url":null,"abstract":"\u0000 In this paper, we present methods for targeted silicon thinning by contour milling to overcome challenges associated with thinning large devices to under 5 µm remaining silicon thickness. Implementation of these techniques are expected to improve the yield of ultra-thin sample preparation and thermal stability of the device through electrical failure analysis for subsequent physical failure analysis. Using a computer numerical controlled milling system, the natural device bow is exploited to thin a specified area of interest by stage tilting before 2D milling. To target a larger area of interests, contour maps are rigged to thin an area preferentially while remaining compatible with existing workflows. Electrical testing have found improved thermal stability of the locally thinned samples over globally thinned samples.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117025797","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Automated Multi-Level Circuit Net Trace for Hotspot Analysis 用于热点分析的自动多级电路网络跟踪
S. Goh
{"title":"Automated Multi-Level Circuit Net Trace for Hotspot Analysis","authors":"S. Goh","doi":"10.31399/asm.cp.istfa2019p0079","DOIUrl":"https://doi.org/10.31399/asm.cp.istfa2019p0079","url":null,"abstract":"\u0000 Post-fault isolation layout net trace and circuit analysis based on abnormal hotspots is a critical step because it directly impacts the outcome of failure analysis. In this work, we review current commercial net tracing solutions in terms of their strengths and drawbacks. As an enhancement, a new net methodology that enables automation and the capability to execute tracing beyond first-level transistors is introduced. This approach could potentially eliminate manual net tracing and significantly improves the overall failure analysis turnaround time.","PeriodicalId":259671,"journal":{"name":"ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-11-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116881259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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