Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing最新文献

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ELsim: a timing simulator for digital CMOS integrated circuits ELsim:用于数字CMOS集成电路的时序模拟器
M. E. Malowany, A. Malowany
{"title":"ELsim: a timing simulator for digital CMOS integrated circuits","authors":"M. E. Malowany, A. Malowany","doi":"10.1109/PACRIM.1989.48439","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48439","url":null,"abstract":"The basic operating principles of ELsim, a timing simulator for digital CMOS circuits, are discussed. ELsim uses the electrical-logic, or ELogic, method where time is solved for rather than voltage and an event-driven, selective trace approach is used which exploits circuit latency to improve simulation speed. Voltage levels at the circuit nodes are descretized, and the size of the voltage steps can be increased to trade accuracy for simulation speed. Results of a comparison of the ELsim simulator performance to that of SPICE for sample CMOS circuits are featured. In general, the delay times and waveforms calculated with ELsim show satisfactorily agreement with those obtained using SPICE.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114353192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Multi-scale dynamic neural net architectures 多尺度动态神经网络架构
L. Atlas, R. Marks, M. Donnell, J. Taylor
{"title":"Multi-scale dynamic neural net architectures","authors":"L. Atlas, R. Marks, M. Donnell, J. Taylor","doi":"10.1109/PACRIM.1989.48413","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48413","url":null,"abstract":"The design of specialized trainable neural network architectures for temporal problems is described. Multilayer extensions of previous dynamic neural net architectures are considered. Two of the key attributes of these architectures are smoothing and decimation between layers. An analysis of parameters (weights) to estimate suggests a massive reduction in training data needed for multiscale topologies for networks with large temporal input windows. The standard back-propagation training rules are modified to allow for smoothing between layers, and preliminary simulation results for these new rules are encouraging. For example, a binary problem with an input of size 32 converged in three iterations with smoothing and never converged when there was no smoothing.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116031139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A general method for the efficient analysis of sensitivities in digital filter designed by linear transformations 线性变换设计的数字滤波器灵敏度分析的一般方法
Du Yuzeng, Xie Qiao
{"title":"A general method for the efficient analysis of sensitivities in digital filter designed by linear transformations","authors":"Du Yuzeng, Xie Qiao","doi":"10.1109/PACRIM.1989.48359","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48359","url":null,"abstract":"A method is presented for fast and accurate calculation of multiplier coefficient sensitivities in linear transformation digital filters. Since the method is based on dealing with analog filter prototypes, it is suitable for all kinds of analog filters. Making use of a general theorem for signal-flow networks, an efficient approach is presented, which is based mainly on the computation of voltages and currents in the analog prototype and its transportation.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134397429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A unified approach for the design of stable 1-D analog and digital filters having variable magnitude characteristics 具有可变幅度特性的稳定一维模拟滤波器和数字滤波器的统一设计方法
C. Gargour, V. Ramachandran, G. Bogdadi
{"title":"A unified approach for the design of stable 1-D analog and digital filters having variable magnitude characteristics","authors":"C. Gargour, V. Ramachandran, G. Bogdadi","doi":"10.1109/PACRIM.1989.48332","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48332","url":null,"abstract":"A unified approach is presented that enables one to design analog and digital filters with variable magnitude characteristics. A basic signal-flow graph is given in which the forward transmittance branch can be a stable filter and the feedback transmittance is a variable constant. As there is a feedback loop, stability of the overall filter has to be ensured, which in turn determines the bounds of the constant in the feedback loop. This is determined by the partial fraction expansion of the ratio of even to odd (or odd to even) polynomials in the analog domain and the ratio of mirror-image to anti-mirror-image polynomials (or its reciprocal) of the denominator polynomial in the digital domain.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"228 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134645249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Minimal and bidirectional fault-tolerant routings for k-hypercube graphs k-超立方图的最小和双向容错路由
K. Kawaguchi, Koichi Wada
{"title":"Minimal and bidirectional fault-tolerant routings for k-hypercube graphs","authors":"K. Kawaguchi, Koichi Wada","doi":"10.1109/PACRIM.1989.48330","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48330","url":null,"abstract":"A communication network G is considered in which a limited number of link and/or node faults F might occur. A routing rho for the network (a fixed path between each pair of nodes) must be chosen without knowing which components might become faulty. The diameter of the surviving route graph R(G, rho )/F (denoted by (D(R(G, rho )/F))), where two nonfaulty nodes are connected by an edge if there are no faults on the route between them, could be one of the fault-tolerant measures for the routing rho . It is shown that for any k(>or=3), there exists a bidirectional and minimal routing (i.e. a routing in which the route between any two nodes (if defined) is assigned to one of the shortest paths between them, and is the same in both directions) lambda /sub k/ on the k-dimensional hypercube graph C/sub k/ such that D(R(C/sub k/, lambda /sub k/)/F)<or=2 for any set of faults F( mod F mod >","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133996436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A simple high frequency CMOS transconductor 一个简单的高频CMOS晶体管
S.P. Singh, J. Hanson, J. Vlach
{"title":"A simple high frequency CMOS transconductor","authors":"S.P. Singh, J. Hanson, J. Vlach","doi":"10.1109/PACRIM.1989.48309","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48309","url":null,"abstract":"A transconductor utilizing only two transistors is presented. It is based upon standard inverter configurations and does not need matching of NMOS and PMOS transistors or of the power supply voltages. The reduction in nonlinearity is achieved by maintaining a zero offset condition. The circuit is not affected by variations in body effect as sources and substrates are connected to fixed voltages. Although the inverter has a low signal level handling capability ( approximately=300 mV for a total harmonic distortion of 1%), it can be improved by utilizing two inverters. This leads to a larger dynamic range and has no noticeable effect on the bandwidth. On the basis of this transconductor, a wideband integrator is developed, with independent adjustment of quality factor and unity-gain frequency.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The effect of optimized devices on the performance of a token ring network interface 优化后的设备对令牌环网络接口性能的影响
S. Stapleton, R. Hardy, M. Deen, R. Fortier, P. Leung, N. Fong
{"title":"The effect of optimized devices on the performance of a token ring network interface","authors":"S. Stapleton, R. Hardy, M. Deen, R. Fortier, P. Leung, N. Fong","doi":"10.1109/PACRIM.1989.48325","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48325","url":null,"abstract":"Results are presented regarding the performance of a token ring network interface adapter, incorporating devices optimized for the network interface application. Previous work has demonstrated the performance improvements possible by using adapter bypass circuitry in the physical layer of the adapter. Here, the operating speed of the token ring is extended by using state-of-the-art device technologies, with devices optimized for this application. The operating speed performance limit of the token ring achievable with these technologies is determined. Three technologies, GaAs, ECL, and high-speed CMOS, are studied. The operating speed limits of the adapter are determined using each of these three technologies. It is shown that the limit is much higher than that presently used.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"45 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126120468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Schur algorithm for Hermitian Toeplitz matrices with singular leading principal submatrices 具有奇异主子阵的厄米特Toeplitz矩阵的Schur算法
C. Zarowski
{"title":"A Schur algorithm for Hermitian Toeplitz matrices with singular leading principal submatrices","authors":"C. Zarowski","doi":"10.1109/PACRIM.1989.48441","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48441","url":null,"abstract":"It is shown to be possible to develop a Schur-type algorithm for Hermitian Toeplitz matrices in the singular case. This algorithm is shown to be amenable to implementation on a parallel processing system consisting of a linear array of O(n) processors. The resulting machine executes the proposed algorithm in O(n) time. It is important to note that the present algorithm and that of Delsarte et al. (1985) are very practical algorithms when the Toeplitz matrix in question has elements over a finite field (as opposed to the field of rational, real, or complex numbers). This is because their is now no problem with errors due to quantization of results.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122304836","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A neural network implementation of the median filter 中值滤波器的神经网络实现
P. Shi, R. Ward
{"title":"A neural network implementation of the median filter","authors":"P. Shi, R. Ward","doi":"10.1109/PACRIM.1989.48414","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48414","url":null,"abstract":"A parallel neural network for finding the median of an array of nonnegative integers is proposed. The processing time of the network is equal to the time delay of five neurons. This is constant irrespective of the number of elements in the array. This is in contrast with the conventional serial and parallel implementations where the delay time increases as the array gets larger. The proposed network makes the real-time enhancement of images and video pictures possible.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124198634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Characterization and simulation of a multi-sampling digital tanlock loop 多采样数字锁环的特性与仿真
J. Bisson, R. Donaldson
{"title":"Characterization and simulation of a multi-sampling digital tanlock loop","authors":"J. Bisson, R. Donaldson","doi":"10.1109/PACRIM.1989.48375","DOIUrl":"https://doi.org/10.1109/PACRIM.1989.48375","url":null,"abstract":"A digital multisampling structure is discussed which follows an analog front end where the sampling rate and number of quantization levels are independently variable. An approach for simulating the loop is presented along with some preliminary performance results. The multisampling digital tanlock loop (MDTL) appears suitable for synchronization of suppressed-carrier data signals. With the exception of the analog front end which is a part of all high-frequency receiver structures, the MDTL can be easily implemented digitally. The phase error distribution is similar to that of a Costas loop which is optimum, in some sense, in additive white Gaussian noise.<<ETX>>","PeriodicalId":256287,"journal":{"name":"Conference Proceeding IEEE Pacific Rim Conference on Communications, Computers and Signal Processing","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1989-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124312404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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