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2007 50th Midwest Symposium on Circuits and Systems最新文献

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Synchronization of two LC-oscillators using nonlinear models 两个lc -振荡器的非线性模型同步
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488631
I. Filanovsky, C. Verhoeven
{"title":"Synchronization of two LC-oscillators using nonlinear models","authors":"I. Filanovsky, C. Verhoeven","doi":"10.1109/MWSCAS.2007.4488631","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488631","url":null,"abstract":"Synchronization of two LC-oscillators is a deeply nonlinear process. We consider synchronization of two van der Pol oscillators using different coupling circuits (four cases are considered), and coupled via first harmonic. We derive the equations for calculation of the synchronization frequency, and the equations for the oscillation amplitudes. It is shown that, in the general case, the synchronization frequency is different from the frequencies of individual oscillators before coupling. The oscillation amplitudes are also not equal: one oscillator becomes a master, and the other oscillator becomes a slave.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124673473","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Reducing misprediction penalty in the Branch Target Buffer 减少分支目标缓冲区中的错误预测惩罚
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488750
S. Abdelhak, A. Sil, Yi Wang, N. Tzeng, M. Bayoumi
{"title":"Reducing misprediction penalty in the Branch Target Buffer","authors":"S. Abdelhak, A. Sil, Yi Wang, N. Tzeng, M. Bayoumi","doi":"10.1109/MWSCAS.2007.4488750","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488750","url":null,"abstract":"Ideal speedup in pipelined processors is seldom achieved due to stalls and breaks in the execution stream. These interrupts are caused by data and control hazards, the latter, however, can be the most detrimental to pipeline performance. Branch Target Buffer (BTB) can reduce performance penalty of branches in pipelined processors by predicting the path of the branch and caching information used by the branch. No stalls will be encountered if the branch entry is found in BTB and the prediction is correct; otherwise, the penalty will be at least two cycles. This paper proposes a novel algorithm based on changing the BTB structure to eliminate the branch misprediction penalty. It also highlights a problem in the previous BTB algorithms (nested branches problem) and proposes a solution to it.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 10-MHz low-power always valid sample-and-hold circuit with low-droop rate 一种10mhz低功耗低时延采样保持电路
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488560
A. Harb, A. Assi
{"title":"A 10-MHz low-power always valid sample-and-hold circuit with low-droop rate","authors":"A. Harb, A. Assi","doi":"10.1109/MWSCAS.2007.4488560","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488560","url":null,"abstract":"A 10 MHz, low-power, high-accuracy fully- differential always-valid sample-and-hold (AVSH) circuit is described. The circuit is based on the high dc gain Miller compensation operational amplifier. Its low- power make it suitable for biomedical application such that implantable smart medical devices (SMDs). The proposed circuit has been designed with CMOS 0.13 mum technology. The simulation shows that at 1.2 V supply voltage and 10 MHz of sampling frequency, the harmonic distortion is less than -52 dB for an input swing of 800 mV @ 2 MHz. The power dissipation is 1.26 mW.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128671701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On amplitude and operating point control of a voltage-controlled crystal oscillator 压控晶体振荡器的幅值和工作点控制
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488575
T. Wey
{"title":"On amplitude and operating point control of a voltage-controlled crystal oscillator","authors":"T. Wey","doi":"10.1109/MWSCAS.2007.4488575","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488575","url":null,"abstract":"In this work, a system architecture is presented for a voltage-controlled crystal oscillator (VCXO) with integrated Pierce structure and varactors in a deep submicron CMOS process. To meet low crystal drive, wide pull range, and negative resistance specifications in a low power supply leads to Pierce VCXO designs requiring both amplitude and operating point regulation. In this design, an automatic amplitude control (AAC) loop and embedded replica bias are implemented with the Pierce cell to provide the required regulation.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127175431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-power and low-complexity architecture for H.264/AVC video decoder H.264/AVC视频解码器的低功耗、低复杂度架构
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488785
Li-Hsun Chen, O. Chen
{"title":"Low-power and low-complexity architecture for H.264/AVC video decoder","authors":"Li-Hsun Chen, O. Chen","doi":"10.1109/MWSCAS.2007.4488785","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488785","url":null,"abstract":"This work proposes an architecture for the H.264/AVC video decoder, of which each functional unit is modularly pipelined and optimized to reduce its hardware complexity. The local buffers are adequately allocated to expedite data communication and to minimize the data access from external memory, thereby to raise computation efficiency and to lower power consumption. By using the cell library of the TSMC 0.25 mum CMOS technology, the proposed hardware core of the H.264/AVC video decoder with a die size of 12.86 mum2 consumes 217.2 mW at 2.5 V and 27 MHz to yield a decoding throughput rate of 30 CIF frames per second. As compared to the conventional H.264/AVC video decoder, the proposed video decoder takes less power and hardware cost.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127488504","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A 0.18μm CMOS 9mW current-mode FLF linear phase filter with gain boost 带增益提升功能的 0.18μm CMOS 9mW 电流模式 FLF 线性相位滤波器
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488828
Xi Zhu, Yichuang Sun, J. Moritz
{"title":"A 0.18μm CMOS 9mW current-mode FLF linear phase filter with gain boost","authors":"Xi Zhu, Yichuang Sun, J. Moritz","doi":"10.1109/MWSCAS.2007.4488828","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488828","url":null,"abstract":"The design and implementation of a CMOS continuous-time follow-the-leader-feedback (FLF) filter is described. The filter is implemented using a fully-differential linear, low voltage and low power consumption operational transconductance amplifier (OTA) based on a source degeneration topology. PSpice simulations using a standard TSMC 0.18 mum CMOS process with 2 V power supply have shown that the cut-off frequency of the filter ranges from 55 MHz to 160 MHz and dynamic range is about 45 dB. The group delay is less than 5% over the whole tuning range; the power consumption is only 9 mW.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130025905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Realization of a GIC using hybrid current conveyor/operational amplifier circuits 用混合电流输送/运算放大器电路实现GIC
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488562
B. Maundy, S. Gift, P. Aronhime
{"title":"Realization of a GIC using hybrid current conveyor/operational amplifier circuits","authors":"B. Maundy, S. Gift, P. Aronhime","doi":"10.1109/MWSCAS.2007.4488562","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488562","url":null,"abstract":"In this paper, a general impedance converter that employs current conveyors and operational amplifier circuits is proposed. The circuit is a hybrid of an operational amplifier and a current conveyor with three passive elements, and offers advantages over conventional current conveyor implementations in its ability to produce high quality factor inductors. Experimental and PSPICE simulation results are presented which verify the theoretical derivations.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"159 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128917232","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Beating the power limit of LC oscillators 超过LC振荡器的功率限制
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488625
Zhongtao Fu, A. Pappu, A. Apsel
{"title":"Beating the power limit of LC oscillators","authors":"Zhongtao Fu, A. Pappu, A. Apsel","doi":"10.1109/MWSCAS.2007.4488625","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488625","url":null,"abstract":"This paper presents a novel LC oscillator topology that requires lower minimum power for startup than other LC oscillators. The Gm-boosted LC oscillator topology introduced here can drop the power required to start an oscillation by 35% in a 0.18 mum CMOS process, without significant degradation in phase noise levels compared to a standard LC oscillator. Such an oscillator may be useful in low power, low noise communication transceivers.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129012276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Design of two-dimensional digital filters having monotonic amplitude-frequency responses using Darlington-type gyrator networks 利用达林顿型陀螺网络设计具有单调幅频响应的二维数字滤波器
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488652
M. Salam, V. Ramachandran
{"title":"Design of two-dimensional digital filters having monotonic amplitude-frequency responses using Darlington-type gyrator networks","authors":"M. Salam, V. Ramachandran","doi":"10.1109/MWSCAS.2007.4488652","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488652","url":null,"abstract":"This paper develops a design of two-dimensional (2- D) stable digital filters starting from Darlington-type gyrator networks and then applying the Generalized Bilinear transformation (GBT). The coefficients of the digital transfer function are obtained as functions of gyrator constant (g), in addition to the other impedances. Design examples are given to illustrate the usefulness of the proposed technique.","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"255 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122364132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fast adder design in dynamic logic 动态逻辑快速加法器设计
2007 50th Midwest Symposium on Circuits and Systems Pub Date : 2007-08-01 DOI: 10.1109/MWSCAS.2007.4488706
V. Navarro-Botello, J. Montiel-Nelson, S. Nooshabadi
{"title":"Fast adder design in dynamic logic","authors":"V. Navarro-Botello, J. Montiel-Nelson, S. Nooshabadi","doi":"10.1109/MWSCAS.2007.4488706","DOIUrl":"https://doi.org/10.1109/MWSCAS.2007.4488706","url":null,"abstract":"This paper presents the design of fast adder structures using a new CMOS logic family - feedthrough logic (FTL). The FTL is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, FTL based circuits perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power FTL provides for smaller propagation time delay (4.1 times), lower energy consumption (30.1%), and similar combined delay, power consumption and active area product (0.9% worst).","PeriodicalId":256061,"journal":{"name":"2007 50th Midwest Symposium on Circuits and Systems","volume":"363 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132973157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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