2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)最新文献_第2页

Coplanar Waveguide Fed Roof-Shaped Multiband Antenna for WPAN Applications 用于WPAN的共面波导馈源屋顶型多波段天线

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802137

L. Tan, Cheng Yanhuan, Weijia Duan, Zhengquan Li

引用次数: 0

A High Linearity and Low Load Regulation LDO with SATEC and TIR Compensation 具有SATEC和TIR补偿的高线性低负载调节LDO

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802344

Siwan Dong, Sen Bu

引用次数: 0

A Novel LDPC Construction Scheme for NAND Flash Memory 一种新型NAND快闪记忆体LDPC建构方案

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802213

Hongyuan Li, Xiaobo Jiang, Zhenghong Yu, Wanjun Zheng

{"title":"A Novel LDPC Construction Scheme for NAND Flash Memory","authors":"Hongyuan Li, Xiaobo Jiang, Zhenghong Yu, Wanjun Zheng","doi":"10.1109/iccss55260.2022.9802213","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802213","url":null,"abstract":"The storage capacity of NAND Flash memory has increased by scaling down to smaller cell size and using multi-level storage technology, but data reliability is degraded by severer retention errors. As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays NAND Flash memory, Low Density Parity Check (LDPC) codes are recently proposed due to their outstanding error correcting capability. Herein, a novel construction scheme of LDPC for NAND Flash memory is proposed. By using the proposed scheme, a high code-rate, high performance of Bit Error Rate (BER), low error floor Quasi Cyclic Low Density Parity Check (QC-LDPC) code is constructed to meet the needs of NAND Flash memory. In the proposed LDPC construction scheme, iterative cycle elimination technique is introduced to ensure that the checksum matrix is cycle-4 free and has minimal cycle-6, which is beneficial to achive high performance of BER and low error floor for high code-rate LDPC. A diagonal coding structure is used in the QC-LDPC code to achieve linear-time coding and meet the high throughput requirements of NAND Flash memory. Simulation results show that NAND Flash memory can be used more 1800 times for Program/Erase (P/E) cycle by using the proposed QC-LDPC codes compared with Euclidean-Geometry LDPC codes. The error floor of the constructed QC-LDPC codes is below 1$0^{-12}$.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131357037","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

ICCSS 2022 Cover Page ICCSS 2022封面

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802390

引用次数: 0

Double-sided Emission of Inverted Quantum-dot Light Emitting Diode by Using Gold Nanowires (AuNW) 利用金纳米线(AuNW)实现反向量子点发光二极管的双面发射

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802228

Ahmad Raza, Fawad Saeed, Sajid Hussain, Abida Perveen, A. Asghar, N. Din, Qasim Khan, W. Lei

{"title":"Double-sided Emission of Inverted Quantum-dot Light Emitting Diode by Using Gold Nanowires (AuNW)","authors":"Ahmad Raza, Fawad Saeed, Sajid Hussain, Abida Perveen, A. Asghar, N. Din, Qasim Khan, W. Lei","doi":"10.1109/iccss55260.2022.9802228","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802228","url":null,"abstract":"Research towards Quantum Dots (QDs) derived from CdSe/ZnS has attracted worldwide attention because of its exceptional optoelectronic properties and use in quantum dots-based light emitting diodes. Usually, a highly conductive electron-transport layer along with hole-transporting layers (HTLs) having low-mobility, and a vacuum-deposited opaque metal electrode are used in the inverted CdSe/ZnS-based QLED. Because of this structure, unbalanced charge injection into the emissive layer occurs, affecting the device's output luminance and stability. Additionally, the fabrication process is more challenging, costly, and time-consuming when using the vacuum-deposition approach. In order to address all of these issues, we used a non-vacuum technique for fabricating an all-solution processable double-sided emitting inverted QLED with a cascade structure and a transparent gold nanowire (AuNW) electrode to obtain emission at the top-side. According to the results, the fabricated QLED had a low turn-on voltage of 2.2 V, luminance of 3905 cd m-2, high current efficiency of 5.9 cd A-1 and a 3.4 % external quantum efficiency. Double-sided QLED devices with AuNW electrode might lead to new lighting and display technologies, according to the findings of this study.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127939288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Cross-shaped Vertical Vacuum Channel Transistor 一种十字形垂直真空通道晶体管

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802313

Zhao Jin, Zhuoya Zhu, Wei Lei, Yi Xie

引用次数: 0

Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET 高导热材料与GAA MOSFET相结合的热感知IC芯片设计

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802341

Young Suh Song, Shubham Tayal, Dr. Shiromani Balmukund Rahi, J. Kim, A. Upadhyay, Byung-Gook Park

{"title":"Thermal-Aware IC Chip Design by Combining High Thermal Conductivity Materials and GAA MOSFET","authors":"Young Suh Song, Shubham Tayal, Dr. Shiromani Balmukund Rahi, J. Kim, A. Upadhyay, Byung-Gook Park","doi":"10.1109/iccss55260.2022.9802341","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802341","url":null,"abstract":"The high integration of integrated circuit (IC) chip design has made thermal-aware design as one of the first priorities of the modern IC chip industry. Even though the modern IC chip technologies have aimed to achieve thermal stability by optimizing circuit design, the rapidly growing integration requires thermal-aware design not only in circuit level but also in transistor level. Such thermal-aware design with bottom-up (from the transistor level to the packaging level) can be used to reliable IC chips. Moreover, since aluminum oxide (Al2O3, also known as alumina) is compatible with CMOS fabrication process and has excellent thermal conductivity, it is possible to efficiently accomplish the improved thermal-aware design. Specifically, Al2O3 has 59 times thermal conductivity compared to HfO2, and 19 times thermal conductivity compared to SiO2. In this paper, considering the outstanding thermal characteristics of Al2O3 we propose a comprehensive improvement including thermal characteristics by combining Al2O3 and GAA MOSFET. As a result, the maximum lattice temperature ($T_{max}$) in transistor has been significantly improved from 624 K to 518 K. In addition, capacitance of transistor could be also decreased, which will give benefits to inverter delay and three-stage ring oscillator (RO3) delay in IC chip.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115393952","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Low-cost, Light-weight Scalable Soft Data Glove for VR Applications 用于VR应用的低成本，轻量级可扩展的软数据手套

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802272

Yier Xia, Wenqian Li, Shengshun Duan, Wei Lei, Jun Wu

引用次数: 4

Design and Implementation of A High-Precision Low-Power Instrumentation Amplifier 一种高精度低功耗仪表放大器的设计与实现

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802338

Xueting Zhao, Xinpeng Xing, Gaofeng Luan, Zhengzhong Wu, Zhihua Wang

引用次数: 0

A Wireless Universal Brain-Machine Interface (BMI) System for Epileptic Diseases 用于癫痫疾病的无线通用脑机接口(BMI)系统

2022 5th International Conference on Circuits, Systems and Simulation (ICCSS) Pub Date : 2022-05-13 DOI: 10.1109/iccss55260.2022.9802412

Kefan Qin, Wei Ma, Chang-chen Hu, Guobin Shuai, Weibo Hu

{"title":"A Wireless Universal Brain-Machine Interface (BMI) System for Epileptic Diseases","authors":"Kefan Qin, Wei Ma, Chang-chen Hu, Guobin Shuai, Weibo Hu","doi":"10.1109/iccss55260.2022.9802412","DOIUrl":"https://doi.org/10.1109/iccss55260.2022.9802412","url":null,"abstract":"This paper presents a wireless universal brain-machine interface (BMI) system. The proposed system integrates three main modules, including an electroencephalogram (EEG) signal analyzer, a neural stimulator, and a PC user interface. Its functionalities include EEG signal acquisition, digital signal processing, electrical stimulation and so on. It can continuously monitor EEG signal status in real time, quickly diagnose brain abnormal activities and correctly generate a proper stimulation if needed. In the EEG signal analyzer, the EEG signal acquisition pathway consists of a four-channel analog front-end featuring high gain and high CMRR. Under the control of an MCU, EEG data are transmitted to the PC in real time through a Bluetooth connection. Then the PC analyzes the EEG signals through the algorithm based on the new Teager energy operator and multiscale entropy. The neural stimulator can provide both positive and negative current stimulations which have programmable pulse width and frequency. Experiment results show that the neural stimulator can generate ±1 mA stimulation current output at ±5 V supply voltage.","PeriodicalId":254992,"journal":{"name":"2022 5th International Conference on Circuits, Systems and Simulation (ICCSS)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-05-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128191521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2