2011 Electronic System Level Synthesis Conference (ESLsyn)最新文献

Increasing computational density of application-specific systems 增加特定应用程序系统的计算密度

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952293

Michael D. Wilder, R. Rinker

{"title":"Increasing computational density of application-specific systems","authors":"Michael D. Wilder, R. Rinker","doi":"10.1109/ESLSYN.2011.5952293","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952293","url":null,"abstract":"Application-specific systems are increasingly being deployed on reconfigurable computing platforms such as the field-programmable gate array (FPGA). These systems can integrate many disparate computing elements, and often contain soft processors hosting application components. Soft processors are sequential, synchronous devices with low computational density, and are not capable of exploiting the concurrency available on the FPGA. We present a method for increasing the computational density of application-specific systems by eliminating soft processors within these systems. This method eliminates soft processors by replacing programs that would be hosted on soft processors with custom, self-contained, circuitizable finite-state machine with datapath (FSMD) components that are automatically generated. We show that FS-MDs produced using this method eliminate the computational overhead associated with fetching and decoding instructions. We further show that this method, when applied to interrupt-driven programs, can produce concurrent FSMDs that arbitrate for shared datapath resources. We discuss how these FSMDs are capable of leveraging the spatial computational capabilities of the FPGA and are therefore more aptly suited for deployment within application-specific systems. We show that these FSMDs eliminate overhead associated with interrupt context switching, decrease interrupt servicing latencies, and eliminate interrupt livelock. We discuss implications and limitations of this method, and describe a prototype that implements the method for programs targeted for the Intel 8051.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123727521","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A framework for generic HW/SW communication using remote method invocation 使用远程方法调用的通用硬件/软件通信框架

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952289

Philipp A. Hartmann, K. Gruttner, Philipp Ittershagen, A. Rettberg

{"title":"A framework for generic HW/SW communication using remote method invocation","authors":"Philipp A. Hartmann, K. Gruttner, Philipp Ittershagen, A. Rettberg","doi":"10.1109/ESLSYN.2011.5952289","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952289","url":null,"abstract":"Implementation of communication between different tasks of a concurrent embedded system is a challenging problem. The aim of our work is to support the refinement and relocation of tasks onto different execution units, such as processors running different operating system or even dedicated hardware. For this purpose communication should be transparent and as independent as possible from the underlying middleware or embedded operating system. Moreover, communication should also be transparent accros the HW/SW boundary. In this work we present a generic framework for seamless communication of (software) tasks with shared resources, called Shared Objects. Communication is implemented using a method-based interface realizing a Remote Method Invocation (RMI) protocol. Our shared communication resources can either be implemented as dedicated hardware, as shared memory or local tasks. The presented framework is a first step towards the unification of shared resource access based on embedded Linux. The effectiveness of our approach is be evaluated with different task mappings and shared resource access implementation styles.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127673961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Application-specific codesign platform generation for digital mockups in cyber-physical systems 网络物理系统中数字模型的特定应用协同设计平台生成

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952295

Bailey Miller, Frank VahicK, T. Givargis

{"title":"Application-specific codesign platform generation for digital mockups in cyber-physical systems","authors":"Bailey Miller, Frank VahicK, T. Givargis","doi":"10.1109/ESLSYN.2011.5952295","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952295","url":null,"abstract":"The testing of cyber-physical systems requires validating device functionality for a wide range of operating conditions. The environment with which the cyber-physical device interacts, such as lungs for a medical ventilator device or a busy freeway for an autonomous vehicle, may be complex and subsequently difficult to explore all possible configurations. Computer simulations that utilize device and environment behavioral models may be used as a first stage of testing, but at some point development must occur using the real device running in real-time. We present a codesign framework for aiding cyber-physical device development where real devices or prototypes are connected to real-time models that simulate the interacting environment. Such test setups are known as digital mockups and allow for testing environment scenarios that are hard to capture with commonly-used but limited physical mockups. The framework supports model hardware/software codesign to enable models of varying speed and accuracy to be implemented within an embedded processor or as a custom coprocessor circuit on an FPGA. We describe an accompanying tool that generates code templates to reduce the time required to develop digital mockup test setups. We utilize the framework to build a digital mockup test setup for a commercial ventilator, and showcase codesign capabilities by implementing environmental models as both circuits and as instructions on a processor.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131914165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

Enabling the synthesis of very long operation properties 能够合成非常长的操作属性

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952292

Jan Langer, Thomas Horn, U. Heinkel

{"title":"Enabling the synthesis of very long operation properties","authors":"Jan Langer, Thomas Horn, U. Heinkel","doi":"10.1109/ESLSYN.2011.5952292","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952292","url":null,"abstract":"In previous work, the high-level synthesis of operation properties has been proposed. In this work, we improve the existing algorithms in order to allow the synthesis of more efficient hardware models. Especially for very long properties no model could be generated before, because both the runtime of the synthesis process and the amount of used hardware resources were prohibitively high. The proposed improvements are threefold. First, the generated non-deterministic control automaton is replaced by a deterministic automaton using an optimized power set construction algorithm. This significantly reduces the number of registers in the generated model. Second, a property can contain local variables (freeze variables), that capture a value at a specific time step and provide this value throughout a property's life span. The scheduling of storage registers for these variables has been optimized. The last improvement merges equivalent assignments to output or state variables (commitments). The merging avoids not only the generation of redundant hardware resources but also simplifies the output multiplexer of the model. Finally, a case study is presented that involves an industrial design of a framer component. The design properties describe the processing of a complete data frame of 19440 cycles length. High-level synthesis and subsequent logic synthesis have been successful and show that the design methodology and synthesis algorithms result in a design with resource usage similar to the industrial component.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125427591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Unifying process networks for design of cyber physical systems 统一网络物理系统设计过程网络

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952280

C. Grimm, Jiong Ou

引用次数: 4

From design-time concurrency to effective implementation parallelism: The multi-clock reactive case 从设计时并发性到有效的实现并行性:多时钟响应性案例

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952287

V. Papailiopoulou, D. Potop-Butucaru, Y. Sorel, R. De Simone, L. Besnard, J. Talpin

引用次数: 16

A hardware/software codesign template library for design space exploration 用于设计空间探索的硬件/软件协同设计模板库

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952279

P. Brunmayr, Jan Haase, C. Grimm

引用次数: 2

Kahn process networks applied to distributed heterogeneous HW/SW cosimulation Kahn过程网络在分布式异构软硬件协同仿真中的应用

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952290

Dylan Pfeifer, J. Valvano

引用次数: 7

Just-in-time compilation for FPGA processor cores FPGA处理器核心的实时编译

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952282

Andrew Becker, Scott Sirowy, F. Vahid

{"title":"Just-in-time compilation for FPGA processor cores","authors":"Andrew Becker, Scott Sirowy, F. Vahid","doi":"10.1109/ESLSYN.2011.5952282","DOIUrl":"https://doi.org/10.1109/ESLSYN.2011.5952282","url":null,"abstract":"Portability benefits have encouraged the trend of distributing applications using processor-independent instructions, a.k.a. bytecode, and executing that bytecode on an emulator running on a target processor. Transparent just-in-time (JIT) compilation of bytecode to native instructions is often used to increase application execution speed without sacrificing portability. Recent work has proposed distributing FPGA circuit applications in a SystemC bytecode to be emulated on a processor with portions possibly dynamically migrated to custom bytecode accelerator circuits or to native circuits on the FPGA. We introduce a novel JIT compiler for bytecode executing on a soft-core FPGA processor. During an iterative process of JIT compiler and emulator architecture codesign, we added JIT-aware resources on a soft-core processor's surrounding FPGA fabric, including a JIT memory, a signal queue, and an emulation memory controller — all unique to JIT compilation for FPGA processors versus traditional processors. Experiments show that regular JIT compilation achieved 3.0× average speedup over emulation, while our JIT-aware FPGA resources yielded an additional 5.2× average speedup, for a total of 15.7× average speedup, at a cost of 21% of a MicroBlaze processor core's slice usage.","PeriodicalId":253939,"journal":{"name":"2011 Electronic System Level Synthesis Conference (ESLsyn)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131908211","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A unifying interface abstraction for accelerated computing in sensor nodes 一种用于加速传感器节点计算的统一接口抽象

2011 Electronic System Level Synthesis Conference (ESLsyn) Pub Date : 2011-06-05 DOI: 10.1109/ESLSYN.2011.5952296

Srikrishna Iyer, Jingyao Zhang, Yaling Yang, P. Schaumont

引用次数: 6