2010 International Symposium on System on Chip最新文献

A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography 基于超椭圆曲线密码的认证协议的灵活集成密码处理器

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625557

Alexander Klimm, M. Haas, O. Sander, J. Becker

{"title":"A flexible integrated cryptoprocessor for authentication protocols based on hyperelliptic curve cryptography","authors":"Alexander Klimm, M. Haas, O. Sander, J. Becker","doi":"10.1109/ISSOC.2010.5625557","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625557","url":null,"abstract":"An integrated cryptographic processor for public key cryptography for embedded systems is proposed in this contribution. The architecture is designed for computational intensive applications based on hyperelliptic curve cryptography (HECC) in the automotive domain. Authentication protocols based on HECC can be adapted for access control systems and demobilizer applications in today's cars. They can raise the security level of these systems, but ask for more computation power than is available in current automotive platforms. Good programmability of the system in high level languages such as C eases the integration of the proposed platform into existing systems and development flows in the automotive domain. In order to include such a level of abstraction a software programmable application specific processor was developed. This processor allows to hide the complex hardware of HECC and avoids a long term hardware development in case of a re-design. The benefit of a software based system combined with a specialized hardware is provided with the described approach. The presented work therefore follows the novel methodology of hardware software codesign where the benefits of both development methodologies are combined in the final system. Experiments show that a substantial gain in computation speed can be achieved while keeping the gate count low.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Correct and energy-efficient design of SoCs: The H.264 encoder case study 正确且节能的soc设计:H.264编码器案例研究

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625558

A. Abdallah, A. Gamatie, J. Dekeyser

引用次数: 16

Homogeneous MPSoC as baseband signal processing engine for OFDM systems 同质MPSoC作为OFDM系统的基带信号处理引擎

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625562

Roberto Airoldi, F. Garzia, Omer Anjum, J. Nurmi

引用次数: 20

Heap access optimizations for a hardware-accelerated Java virtual machine 硬件加速Java虚拟机的堆访问优化

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625548

Joonas Tyystjärvi, T. Säntti, J. Plosila

引用次数: 0

Multiprocessor system and software design for distributed control applications 分布式控制应用的多处理器系统和软件设计

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625533

S. Chakraborty

引用次数: 0

Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis 利用指令缓冲器并经过调度分析，降低了指令存储器的能耗

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625536

V. Guzma, Teemu Pitkänen, J. Takala

{"title":"Reducing instruction memory energy consumption by using Instruction Buffer and after scheduling analysis","authors":"V. Guzma, Teemu Pitkänen, J. Takala","doi":"10.1109/ISSOC.2010.5625536","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625536","url":null,"abstract":"Use of Instruction Buffers (also named Repeat Buffers), and caches is common way to avoid memory speed bottleneck in presence of memory hierarchies. Once the instruction resides in a cache or a buffer, repeated execution of the same instruction does not require separate memory access and possible cache miss. Use of the instruction buffers offer also an advantage when low energy consumption is an issue. Reading instruction from the buffer requires order of magnitude less energy then fetch from instruction memory. Keeping memories in the deselect mode and fetching data from the buffer takes roughly half of the power compared to the reading from the memory. In this work, we analyze effects of adding instruction buffer to an existing ASIP architecture. We analyze already generated code of an application, to find the often executed loops, and augment instructions with instruction buffer control information. We show, that for many of embedded applications, storing kernels of execution in the instruction buffer saves between 60 to 87% of instruction memory, even with most trivial loops. This savings can translate to up to 47% reduction of memory energy.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125365586","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Efficient compensation of delay variations in high-speed network-on-chip data links 高速片上网络数据链路中时延变化的有效补偿

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625534

S. Höppner, D. Walter, H. Eisenreich, R. Schüffny

引用次数: 5

Process variation and layout mismatch tolerant design of source synchronous links for GALS networks-on-chip GALS片上网络源同步链路的工艺变化与容错设计

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625539

Alessandro Strano, Carles Hernández, F. Silla, D. Bertozzi

引用次数: 4

Hybrid on-chip clocking for sensor nodes 用于传感器节点的混合片上时钟

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625540

Spencer S. Kellis, N. Gaskin, Bennion Redd, E. Marsman, Richard B. Brown

引用次数: 2

Program image dissemination protocol for low-energy multihop wireless sensor networks 低能量多跳无线传感器网络的程序图像传播协议

2010 International Symposium on System on Chip Pub Date : 2010-11-09 DOI: 10.1109/ISSOC.2010.5625550

Lasse Määttä, J. Suhonen, Teemu Laukkarinen, T. Hämäläinen, Marko Hännikäinen

{"title":"Program image dissemination protocol for low-energy multihop wireless sensor networks","authors":"Lasse Määttä, J. Suhonen, Teemu Laukkarinen, T. Hämäläinen, Marko Hännikäinen","doi":"10.1109/ISSOC.2010.5625550","DOIUrl":"https://doi.org/10.1109/ISSOC.2010.5625550","url":null,"abstract":"A Wireless Sensor Network (WSN) consists of programmable, low-cost and resource-constrained nodes. Adding new features or error fixes requires reprogramming nodes. Manually reprogramming hundreds or thousands of nodes is impractical as it takes significant effort and time. Therefore, WSNs require a mechanism for updating the nodes program image, which contains the applications and protocols running on each node. Current protocols for updating program images rely on a large external memory that is used to temporary store program images. In this paper we present the design, implementation and experimental measurements of a lightweight and reliable Program Image Dissemination Protocol (PIDP) for autonomous adhoc multihop WSNs. PIDP requires no external memory storage, is independent of the WSN stack, offers a low overhead protocol for transferring program images, and can reprogram the whole WSN stack. An update procedure with PIDP in one part of the network does not interfere with the WSN elsewhere. PIDP was implemented on a node platform with an 8-bit 2 MIPS Microchip PIC18LF8722 microcontroller and a 2.4 GHz Nordic Semiconductors nRF24L01 radio. PIDP requires less than 7 kilobytes of program memory and from 22 to 815 bytes of data memory. In experiments PIDP reprogrammed a campus WSN, which is a running deployment of 178 nodes, in 5 hours.","PeriodicalId":252669,"journal":{"name":"2010 International Symposium on System on Chip","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131023857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11