{"title":"CMOS-Memristive Analog Multiplier Design","authors":"Ileskhan Kalysh, O. Krestinskaya, A. P. James","doi":"10.1109/coconet.2018.8476883","DOIUrl":"https://doi.org/10.1109/coconet.2018.8476883","url":null,"abstract":"The implementation of analog multiplication process in analog domain is a challenging task, which involves complex circuits with large on-chip area and high power consumption to achieve highly linear multiplication performance. Therefore, such multipliers cannot be used for large scale problems. This paper addresses these issues and proposes four quadrant analog CMOS-memristive analog multiplier design aiming to reduce on-chip area and power consumption of the circuit. The multiplier is designed using TSMC 180 nm CMOS technology and simulated in SPICE. The proposed multiplier allows to reduce on-chip area and power consumption by 25% and 5%, respectively.","PeriodicalId":250788,"journal":{"name":"2018 International Conference on Computing and Network Communications (CoCoNet)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122840824","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Meirambek Mukhametkhan, O. Krestinskaya, A. P. James
{"title":"Analysis of Multilayer Perceptron with Rectifier Linear Unit Activation Function","authors":"Meirambek Mukhametkhan, O. Krestinskaya, A. P. James","doi":"10.1109/coconet.2018.8476902","DOIUrl":"https://doi.org/10.1109/coconet.2018.8476902","url":null,"abstract":"The implementation of analog neural network and online analog learning circuits based on memristive crossbar has been intensively explored in the recent years. The design of various activation functions is important for neuromorphic circuits and systems, especially deep leaning neural networks. There are several implementations of sigmoid and tangent activation function, while the analog hardware implementation of the neural networks with linear activation functions is an open problem. Therefore, this paper introduces a multilayer perceptron design with linear activation function using TSMC $130 mu m$CMOS technology. In this paper, the performance of the proposed linear activation function is illustrated. In addition, the temperature variation and noise analysis are shown.","PeriodicalId":250788,"journal":{"name":"2018 International Conference on Computing and Network Communications (CoCoNet)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127328263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Variability Analysis of Memristor-based Sigmoid Function","authors":"N. Kaiyrbekov, O. Krestinskaya, A. P. James","doi":"10.1109/coconet.2018.8476878","DOIUrl":"https://doi.org/10.1109/coconet.2018.8476878","url":null,"abstract":"Activation functions are widely used in neural networks to decide the activation value of the neural unit based on linear combinations of the weighted inputs. The effective implementation of activation function is highly important to enhance he performance of a neural network. One of the most widely used activation functions is sigmoid. Therefore, there is a growing interest to enhance the performance of sigmoid circuits. In this paper, the main objective is to modify existing current mirror based sigmoid model by replacing CMOS transistors with memristive devices. We present the performance, variation of transistor sizes and temperature. The area, power and noise in the modified CMOS-memristive sigmoid circuit are shown. The application of memristors in the sigmoid circuit ensures the reduction of on-chip area, and power dissipation by 7%. The proposed sigmoid circuit was simulated in SPICE using TSMC 180nm CMOS design process.","PeriodicalId":250788,"journal":{"name":"2018 International Conference on Computing and Network Communications (CoCoNet)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128153533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Analysis of Noise in Current Mirrors with memristive Device","authors":"Nazerke Kulmukhanova, I. Dolzhikova","doi":"10.1109/coconet.2018.8476813","DOIUrl":"https://doi.org/10.1109/coconet.2018.8476813","url":null,"abstract":"This work presents an analysis of noise in a cascode current mirror with CMOS-memristive device done by comparison with the basic current mirror. The analysis is completed based on THD for different frequency and channel length values by means of computer-aided design. AC and DC analyses are presented for both balanced and unbalanced current mirrors. While the change in the channel length has similar effect in both circuits, at high frequencies the memristive circuit is less susceptible to noise.","PeriodicalId":250788,"journal":{"name":"2018 International Conference on Computing and Network Communications (CoCoNet)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116539237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of True Random Number Generator based on Double-Scroll Attractor circuit with GST memristor emulator","authors":"Togzhan Abzhanova, I. Dolzhikova, A. P. James","doi":"10.1109/COCONET.2018.8476899","DOIUrl":"https://doi.org/10.1109/COCONET.2018.8476899","url":null,"abstract":"The cryptographic security provided by various techniques of random number generator (RNG) construction is one of the developing research areas today. Among various types of RNG, the true random bit generator (TRBG) can be considered as the most unpredictable and most secure because its randomness seed is generated from chaotic sources. This paper proposes a design of TRBG model based on double-scroll attractors circuits with GST memristor. After implementation and simulation of the chaotic circuit with GST memristor emulator, the chaotic behavior of the output voltage and inductor current were received. Moreover, their dependence on the input voltage revealed the close to double-scroll form. The randomness generated from the proposed circuit was tested by analysis of the Fast Fourier Transform (FFT) and Lyapunov exponents of the output voltage.","PeriodicalId":250788,"journal":{"name":"2018 International Conference on Computing and Network Communications (CoCoNet)","volume":"124 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134392871","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Implementation of Memristor in Bessel filter with RLC components","authors":"Galymzhan Torebayev, A. Nandakumar","doi":"10.1109/COCONET.2018.8476913","DOIUrl":"https://doi.org/10.1109/COCONET.2018.8476913","url":null,"abstract":"The Bessel filters are optimized to collect competent transient response due to a linear phase in the passband. In other words, during the filtering process, there will be comparatively impoverished frequency response with lower amplitude inequity. Memristor is asserted as a passive, two-terminal essential component of the circuit and the use of such element in schemes as an adjustable resistance allows the realization of memory-resistor based analog circuits, which achieve the wide range of specific parameters. The application of RLC circuit for Bessel filter prototype is theoretically expected to behave in a positive way, however, the further simulations with software and analysis of the results will reveal the nature of the effect.","PeriodicalId":250788,"journal":{"name":"2018 International Conference on Computing and Network Communications (CoCoNet)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121993039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}