2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)最新文献

Programming models for reconfigurable manycore systems 可重构多核系统的编程模型

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533897

D. Andrews, M. Platzner

引用次数: 8

A programming model for reconfigurable computing based in functional concurrency 基于函数并发的可重构计算编程模型

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533911

W. Harrison, I. Graves, A. Procter, M. Becchi, G. Allwein

引用次数: 6

A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip 非对称三维片上网络设计空间探索仿真环境

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533908

J. Joseph, Sven Wrieden, Christopher Blochwitz, A. Ortiz, Thilo Pionteck

{"title":"A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip","authors":"J. Joseph, Sven Wrieden, Christopher Blochwitz, A. Ortiz, Thilo Pionteck","doi":"10.1109/ReCoSoC.2016.7533908","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533908","url":null,"abstract":"We present a comprehensive simulation environment for design space exploration in Asymmetric 3D-Networks-on-chip (A-3D-NoCs) covering the heterogeneity in 3D-System-on-chips (3D-SoCs). A challenging aspect of A-3D-NoC design is the consideration of interwoven parameters of the communication infrastructure and characteristics of the manufacturing technologies. Thus, simultaneous evaluation of multiple design metrics is mandatory. Our simulation environment consists of three parts. First, it comprises a NoC simulator that supports a multitude of different manufacturing technologies, router architectures, and network topologies within a single design. As a key feature, the NoC and technologies parameters per chip layer are fully configurable during simulation runtime permitting flexible and fast evaluation. Second, a central reporting tool facilitates system analysis on different abstraction levels. Third, the evolution tool provides various synthetic and real-world based benchmarks. Thus, our tool allows for an incremental approach to systematically explore the A-3D-NoC's design space.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"283 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123554406","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 8

Towards risk aware NoCs for data protection in MPSoCs 在mpsoc中建立具有风险意识的noc以保护数据

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533898

Martha Johanna Sepúlveda, Daniel Flórez, Ramon Fernandes, C. Marcon, G. Gogniat, G. Sigl

引用次数: 5

Dynamic spatially isolated secure zones for NoC-based many-core accelerators 基于网络的多核加速器的动态空间隔离安全区域

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533900

M. M. Real, P. Wehner, Vincent Migliore, Vianney Lapôtre, D. Göhringer, G. Gogniat

{"title":"Dynamic spatially isolated secure zones for NoC-based many-core accelerators","authors":"M. M. Real, P. Wehner, Vincent Migliore, Vianney Lapôtre, D. Göhringer, G. Gogniat","doi":"10.1109/ReCoSoC.2016.7533900","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533900","url":null,"abstract":"Many-core architectures are becoming a major execution platform in order to face the increasing number of applications executed in parallel. While these architectures provide massive parallelism and high performance to the users, they also introduce key challenges in terms of security. Indeed, in order to leverage performance, a great number of applications running in parallel may share resources. A malicious application may compromise other applications sharing common resources or the whole system by directly accessing, deducing or retrieving sensitive data. This work focuses on a many-core accelerator architecture extended with mechanisms allowing the logical and spatial isolation of sensitive applications through the dynamic creation of secure zones. Each sensitive application is executed within a secure zone avoiding any resource sharing with other potentially malicious applications, preventing denial of services within the secure zones as well as confidentiality and integrity attacks. A set of services guarantying the dynamic creation and handling of spatially isolated secure zones in a many-core accelerator architecture is proposed. These services are integrated into a software controller on a many-core accelerator architecture and evaluated through virtual prototyping.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129783299","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 12

SoCDep2: A framework for dependable task deployment on many-core systems under mixed-criticality constraints SoCDep2:用于在混合临界约束下在多核心系统上可靠部署任务的框架

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533903

Siavoosh Payandeh Azad, Behrad Niazmand, P. Ellervee, J. Raik, G. Jervan, T. Hollstein

引用次数: 5

The selector-tree network: A new self-routing and non-blocking interconnection network 选择器树网络:一种新的自路由、无阻塞互联网络

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533894

Tripti Jain, K. Schneider, Anoop Bhagyanath

引用次数: 3

A programmable and reconfigurable core for binary image processing 用于二进制图像处理的可编程和可重构核心

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533912

Ayad Dalloo, A. Ortiz

{"title":"A programmable and reconfigurable core for binary image processing","authors":"Ayad Dalloo, A. Ortiz","doi":"10.1109/ReCoSoC.2016.7533912","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533912","url":null,"abstract":"Binary-image processing cores are extremely useful in many image and video applications such as object recognition, tracking, motion detection, and identification. To address the variety of applications and binary-image kernels, we propose an FPGA-based intellectual property core with enhanced flexibility: it is programmable, reconfigurable, and parameterizable. The core performs single binary image kernels (morphological operations) and even complete algorithms composed by sequences of operations; the algorithms' control does not require an external processor as in previous approaches. The reconfiguration features allow adapting the image size, structuring element, and even image parallelism for some operations at run-time. Finally, the parameterization allows defining the maximum image, feature, and command-buffer sizes as well as the number of pixel processing units at compile time. The careful combination of programmability, reconfigurability, and parameterization produces a flexible yet efficient binary-image processing architecture. A detailed experimental validation using a Virtex 5 platform assesses the advantages of the proposed architecture versus previous approaches. The results show that the core can process about 1500 frames per second for 32 operations for a 1024 × 1024 image and 5×5 structure-element at 100MHz frequency. The results demonstrate that the core is suitable for real-time binary image processing applications.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"885 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134401723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Online reconfigurable routing method for handling link failures in NoC-based MPSoCs 基于noc的mpsoc中处理链路故障的在线可重构路由方法

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533905

Poona Bahrebar, D. Stroobandt

引用次数: 1

Analysis of radiation-induced SEUs on dynamic reconfigurable systems 动态可重构系统辐射诱导seu分析

2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC) Pub Date : 2016-06-27 DOI: 10.1109/ReCoSoC.2016.7533907

L. Sterpone, L. Boragno, D. M. Codinachs

{"title":"Analysis of radiation-induced SEUs on dynamic reconfigurable systems","authors":"L. Sterpone, L. Boragno, D. M. Codinachs","doi":"10.1109/ReCoSoC.2016.7533907","DOIUrl":"https://doi.org/10.1109/ReCoSoC.2016.7533907","url":null,"abstract":"SRAM-Based FPGAs are widely employed in space and avionics computing. The unfriendly environment and FPGA radiation sensibility can have dramatic drawbacks on the application reliability. The partial self-reconfiguration ability gives an excellent aid to counteract single event upsets (SEUs) caused by excessive silicon ionization, and the consequent system misbehavior. Related to this feature, fault injection and fault emulation and configuration scrubbing, has been carried out over three versions of a reconfigurable Fast Fourier Transform (FFT) system: a single FFT, a single larger FFT and a FFT with TMR architecture. The analysis has been focused on multiple injected SEUs scenario, considering the availability problem in a real-time application and highlighting the circuit tolerance at the upset presence. This operation has the goal to emulate as much as possible a real radiation test avoiding all the handicaps that this procedure involves. The obtained results have shown the advantages of the configuration scrubbing performed with the aim to fix multiple upsets, achieving up to 13.6% of circuit hardening. The achieved conclusions are an interesting starting point for the study of fault mitigation techniques through the use of reconfiguration. The projects have been tested on a Z-7010 AP SoC.","PeriodicalId":248789,"journal":{"name":"2016 11th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2016-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116503331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4