Programming models for reconfigurable manycore systems

Abstract

Our semiconductor industry is ushering in the era of the reconfigurable manycore chip to increase the energy efficiency of computing irregular parallelism within large and power hungry data centers. If reconfigurable manycores are to become part of the mainstream narrative for next generation data center and warehouse scale computers, the large cadre of software programmers must be given access to these devices through their accepted programming models. In this paper we present an overview of two prior projects called hthreads and ReconOS, that both successfully unified computations that ran as hardware threads in the FPGA with software threads on fixed ISA components under the multithreaded programming model. We discuss the design tradeoffs that were made and resulting implementation details of these two systems. We then project how aspects of both systems may provide important insights for system architectets and system software developers for bringing evolving reconfigurable manycores under the virtualization ecosystems used within datacenters.