A programmable and reconfigurable core for binary image processing

Abstract

Binary-image processing cores are extremely useful in many image and video applications such as object recognition, tracking, motion detection, and identification. To address the variety of applications and binary-image kernels, we propose an FPGA-based intellectual property core with enhanced flexibility: it is programmable, reconfigurable, and parameterizable. The core performs single binary image kernels (morphological operations) and even complete algorithms composed by sequences of operations; the algorithms' control does not require an external processor as in previous approaches. The reconfiguration features allow adapting the image size, structuring element, and even image parallelism for some operations at run-time. Finally, the parameterization allows defining the maximum image, feature, and command-buffer sizes as well as the number of pixel processing units at compile time. The careful combination of programmability, reconfigurability, and parameterization produces a flexible yet efficient binary-image processing architecture. A detailed experimental validation using a Virtex 5 platform assesses the advantages of the proposed architecture versus previous approaches. The results show that the core can process about 1500 frames per second for 32 operations for a 1024 × 1024 image and 5×5 structure-element at 100MHz frequency. The results demonstrate that the core is suitable for real-time binary image processing applications.