2017 75th Annual Device Research Conference (DRC)最新文献_第2页

Novel two-terminal vertical transition metal dichalcogenide based memory selectors 新型双端垂直过渡金属二硫化物存储器选择器

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999429

Feng Zhang, Yuqi Zhu, J. Appenzeller

{"title":"Novel two-terminal vertical transition metal dichalcogenide based memory selectors","authors":"Feng Zhang, Yuqi Zhu, J. Appenzeller","doi":"10.1109/DRC.2017.7999429","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999429","url":null,"abstract":"For resistive random access memory (RRAM) applications, selector devices play an important role to ensure that an individual memory element can be properly addressed through reading and writing while at the same time the information stored in the other cells of the same array does not get perturbed and power does not get wasted by undesirable leakage through unselected cells. An ideal selector device has to fulfill many criteria simultaneously such as: i) it has to support high on-state current densities (∼107 A/cm2), ii) it has to exhibit a large nonlinearity at half bias NL1/2, iii) it should be capable of bidirectional operation, and iv) it should be back-end-of-the-line (BEOL) compatible [1]. Moreover, its operation voltage needs to be compatible with the memory element. In the context of the above, two-terminal devices are desirable for ease of integration, and silicon based diodes, oxide pn-junction diodes and threshold voltage switches, such as metal-insulator-transition (MIT), are candidates that have been explored in the past. However, all of these three types of selector devices suffer from serious drawbacks. For example, two-terminal NPN silicon diodes do not conform to high-density, nonvolatile memories with 3D stack structures due to their high processing temperature between 700°C and 1000°C and the difficulty of growing high-quality epitaxial silicon over metals. Although amorphous silicon can eliminate the need for a single-crystal silicon seed and allows for low processing temperatures of around 800°C, it does not provide the required semiconducting performance. Oxide-based access devices on the other hand can be processed at low temperatures but do not reach the desired on-current levels, while MIT-based selectors cannot provide the desired NL1/2. This makes developing novel types of selectors and ultimately a cell highly desirable.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130313444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

High-temperature p-type polarization doped AlGaN cladding for sub-250 nm deep-UV quantum well LEDs by MBE 高温p型极化掺杂AlGaN包层制备亚250 nm深紫外量子阱led

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999517

S. Bharadwaj, S. Islam, Kevin Lee, Andrew Devine, V. Protasenko, S. Rouvimov, H. Xing, D. Jena

{"title":"High-temperature p-type polarization doped AlGaN cladding for sub-250 nm deep-UV quantum well LEDs by MBE","authors":"S. Bharadwaj, S. Islam, Kevin Lee, Andrew Devine, V. Protasenko, S. Rouvimov, H. Xing, D. Jena","doi":"10.1109/DRC.2017.7999517","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999517","url":null,"abstract":"Deep UV (DUV) light-emitting diodes (LEDs) are finding increased application in many areas including water purification and sterilization. Sub-270 nm emission is ideal for these applications since bacterial DNA absorbs strongly in this wavelength regime. To extract high energy photons (∼5 eV), the LED cladding regions must be transparent and therefore consist of high Aluminum content (>60%) n- and p-AlGaN. Ensuring high electrical conductivity in such cladding regions becomes increasingly difficult with increasing Al content due to the large dopant activation energies, especially for the acceptor dopant, Magnesium (Mg) [1]. To maximize Mg incorporation by MBE, a commonly utilized approach is to grow the p-cladding region at a low temperature (∼630 °C [2]). A low growth temperature causes defects and undesired compositional inhomogeneity, leading to inferior vertical hole transport (Fig. 1). To address these issues, a combination of high temperature MBE growth of the p-AlGaN cladding and polarization-induced doping is employed. While high growth temperature ensures good crystal quality and compositional uniformity for the Al-rich p-AlGaN, the polarization-induced doping compensates for the reduced Mg incorporation at high temperature. A sub-250 nm DUV LED is demonstrated for the first time using MBE-grown p-AlGaN layers at a high temperature of 730 °C. SIMS analysis (Fig. 2) showed that Mg incorporation decreases by ∼5 times over the temperature range from 650–730°C for 75% AlGaN, and that Mg incorporation decreases at high Al content, consistent with thermodynamic principles [3]. Based on the observations from Fig. 1 and 2, a substrate temperature of 730 °C was chosen for the p-cladding layer for a sub-250 nm DUV LED structure.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131837557","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Radiation hardness of Ga2O3 MOSFETs against gamma-ray irradiation Ga2O3 mosfet抗γ射线辐照的辐射硬度

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999400

M. Wong, A. Takeyama, T. Makino, T. Ohshima, K. Sasaki, A. Kuramata, S. Yamakoshi, M. Higashiwaki

{"title":"Radiation hardness of Ga2O3 MOSFETs against gamma-ray irradiation","authors":"M. Wong, A. Takeyama, T. Makino, T. Ohshima, K. Sasaki, A. Kuramata, S. Yamakoshi, M. Higashiwaki","doi":"10.1109/DRC.2017.7999400","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999400","url":null,"abstract":"Gallium oxide (Ga2O3) is attractive for power devices owing to its wide bandgap of 4.5 eV and the availability of economical device-quality native substrates. Research on Ga2O3 Schottky barrier diodes and field-effect transistors (FETs) has seen rapid recent progress [1]. An unexplored area of immense interest is the radiation tolerance of these devices, whose high-voltage and high-temperature capabilities are expected to find applications in extreme radiation environments such as space and nuclear facilities that impose stringent reliability requirements to ensure stable operations. This paper reports the first investigation into the effects of ionizing radiation on Ga2O3 metal-oxide-semiconductor FETs (MOSFETs). A gamma-ray (y-ray) tolerance as high as 230 kGy(SiO2) was demonstrated for the bulk Ga2O3 channel by virtue of the MOSFETs' stable on-current, on-resistance (Ron), and threshold voltage (Vt) against irradiation. Hysteresis in the transfer characteristics remained negligible after exposure to the highest dose. Radiation-induced degradations in the gate insulation and surface passivation, which could be attributed to dielectric damage and interface trap generation, were found to limit the overall radiation resistance of these devices.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115326318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

BEOL compatible 2D layered materials as ultra-thin diffusion barriers for Cu interconnect technology 兼容BEOL的二维层状材料作为Cu互连技术的超薄扩散屏障

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999485

Chun-Li Lo, Shengjiao Zhang, Tingting Shen, J. Appenzeller, Zhihong Chen

引用次数: 8

600 V GaN vertical V-trench MOSFET with MBE regrown channel 带MBE再生沟道的600v GaN垂直V沟道MOSFET

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999414

Wenshen Li, K. Nomoto, Kevin Lee, S. Islam, Zongyang Hu, M. Zhu, Xiang Gao, M. Pilla, D. Jena, H. Xing

{"title":"600 V GaN vertical V-trench MOSFET with MBE regrown channel","authors":"Wenshen Li, K. Nomoto, Kevin Lee, S. Islam, Zongyang Hu, M. Zhu, Xiang Gao, M. Pilla, D. Jena, H. Xing","doi":"10.1109/DRC.2017.7999414","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999414","url":null,"abstract":"GaN vertical power transistors have gained increasing interest in recent years due to the advantages over lateral transistors in high voltage/high current applications. To date, two major topologies have been studied most: gate-on-epi-surface (GoE) and gate-on-sidewall (GoS). The GoE devices include CAVET [1] and VDMOSFET-like transistors [2, 3]. The GoS devices include U-MOS or trench-MOSFETs with inversion channel [4, 5] or regrown AlGaN/GaN semi-polar channel [6], as well as depletion-mode MISFET [7]. The vertical MISFET is the simplest to fabricate, however, it does not have avalanche capabilities inherently besides being difficult to achieve sufficiently large Vth. It is easier for trench MOSFETs to achieve normally-off operation, high breakdown voltage (BV) and small footprint. However, it is challenging to achieve high mobility in the inversion channel. In contrast, CAVETs, VDMOS-like transistors and PolarMOS [3] utilize high mobility AlGaN/GaN channel to achieve low Ron, but the channel regrowth posts challenges in achieving low off-state leakage in un-gated regrowth interface. Recently, a novel design based on trench MOSFET is realized by MOCVD regrowth of a thin GaN interlayer [8]. Low Ron and high BV is achieved in the gated regrown channel. Similar to the other MOCVD regrown devices, the buried Mg-doped p-GaN needs to be re-activated by exposing the p-GaN surface during high temperature anneal. This leads to high thermal budget and poses limitations on device geometry. Furthermore, any incomplete activation of buried p-GaN leads to reduced BV. In this work, we design a V-shaped trench MOSFET with MBE regrown UID GaN channel. −600 V breakdown voltage with normally-off operation is demonstrated without the need for re-activation of the buried p-GaN. To our knowledge, this is the highest BV achieved in GaN vertical transistors with MBE regrown channel.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"36 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114132011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 13

A proposal for a magnetostriction-assisted all-spin logic device 一种磁致伸缩辅助全自旋逻辑器件的设计

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999492

R. M. Iraei, S. Dutta, S. Manipatruni, D. Nikonov, I. Young, J. Heron, A. Naeemi

{"title":"A proposal for a magnetostriction-assisted all-spin logic device","authors":"R. M. Iraei, S. Dutta, S. Manipatruni, D. Nikonov, I. Young, J. Heron, A. Naeemi","doi":"10.1109/DRC.2017.7999492","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999492","url":null,"abstract":"As scaling CMOS devices is approaching its fundamental limits, a new direction of research has emerged to study beyond-CMOS spintronic devices that use electronic spin as their state variable, offering new and enhanced functionalities. Due to low operating voltage, non-volatility, and efficient implementation of majority gate, a novel spin-based device, all-spin logic (ASL), has been widely studied for applications including interconnects [1], pattern recognition systems [2], and Boolean gates [3]. However, ASL relies on a non-local spin valve (NLSV) structure with the connection to ground being close to the input magnet to ensure non-reciprocity. Thus, a large fraction of injected spins is shunted to ground without ever reaching the output magnet. In addition, supply clocking is envisioned to reduce energy dissipation [3]. Even then, a 32-bit addition by ASL compared to that by CMOS, requires 5 orders of magnitude more energy. In this paper, we propose a novel device that uses voltage-controlled strain-mediated magnetization switching [4] and spin transfer torque (STT) to perform the first and second 900 of switching, respectively. The STT is created in a conventional spin valve instead of the NLSV structure used in ASL. Hence, the wasteful shunt path to ground is eliminated. Non-reciprocity is ensured through a clocking scheme in which the input and output magnets are oriented along the stable easy axis and the meta-stable saddle point of energy profile, respectively. It has been shown that the deterministic switching of a magnet from a saddle point is more efficient in terms of delay and energy and affected less by thermal noise [5], [6]. The device can be cascaded in a domino logic scheme, Fig. 1 a, by performing the first 900 switching for all cascaded logic gates simultaneously; therefore, the overall delay of a more complicated circuit like a 32-bit adder significantly improves.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122738823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7

Transparent amorphous oxide semiconductors: Materials design, electronic structure, and device applications 透明非晶氧化物半导体:材料设计、电子结构和器件应用

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999387

H. Hosono

引用次数: 3

Supervised learning in spiking neural networks with MLC PCM synapses 具有MLC - PCM突触的脉冲神经网络的监督学习

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999481

S. Nandakumar, I. Boybat, M. Le Gallo, A. Sebastian, B. Rajendran, E. Eleftheriou

引用次数: 13

There's still plenty of room at the bottom — And at the Top 底部还有很多空间-顶部也是

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999386

T. Liu, Peng Zheng, Sangwan Kim, Kimihiko Kato, V. Stojanović

引用次数: 2

Effect of thermal resistance and scaling on dc-IV characteristics of PCMO based RRAM devices 热阻和结垢对PCMO RRAM器件dc-IV特性的影响

2017 75th Annual Device Research Conference (DRC) Pub Date : 2017-06-25 DOI: 10.1109/DRC.2017.7999428

S. Chouhan, P. Kumbhare, A. Khanna, N. Panwar, U. Ganguly

{"title":"Effect of thermal resistance and scaling on dc-IV characteristics of PCMO based RRAM devices","authors":"S. Chouhan, P. Kumbhare, A. Khanna, N. Panwar, U. Ganguly","doi":"10.1109/DRC.2017.7999428","DOIUrl":"https://doi.org/10.1109/DRC.2017.7999428","url":null,"abstract":"Ionic transport is accelerated by both electric field and temperature [1]. The role of Joule heating in filamentary RRAM devices is well explored [2]. However, Joule heating in non-filamentary RRAM has recently been explored. First, GeSbTe (GST)/PCMO stack showed improved performance, which was phenomenologically explained by proposing the role of GST as a heater element [3]. Recently, our group has proposed self-heating (i.e. heat generated within PCMO) to explain experimental DC [4] and transient [5] IV characteristics supported by quantitative TCAD studies. In this paper, we experimentally study the effect of thermal engineering on the switching characteristics of PCMO based RRAM devices. We modify the thermal resistance of the stack by using different SiO2 thicknesses (Fig. 1). Firstly, we present the effect of different SiO2 thicknesses and device area on the peak device temperature by using MATLAB PDE solver. Secondly, we fabricate devices of various areas on two different SiO2 thicknesses to study the effect on device temperature due to different thermal resistance on the switching characteristics. The qualitative agreement between experiment and thermal simulations indicates the importance of thermal engineering considerations for PCMO RRAM device performance.","PeriodicalId":248087,"journal":{"name":"2017 75th Annual Device Research Conference (DRC)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125087202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 7