2008 International Conference on Application-Specific Systems, Architectures and Processors最新文献_第3页

Buffer allocation for advanced packet segmentation in Network Processors 网络处理器中用于高级数据包分段的缓冲区分配

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580182

Daniel Llorente, Kimon Karras, Thomas Wild, A. Herkersdorf

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引用次数: 3

An efficient method for evaluating polynomial and rational function approximations 一个评估多项式和有理函数近似的有效方法

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580185

N. Brisebarre, S. Chevillard, M. Ercegovac, J. Muller, S. Torres

引用次数: 8

FPGA-based hardware accelerator of the heat equation with applications on infrared thermography 基于fpga的热方程硬件加速器及其在红外热成像中的应用

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580175

F. Pardo, Paula López Martínez, D. Cabello

{"title":"FPGA-based hardware accelerator of the heat equation with applications on infrared thermography","authors":"F. Pardo, Paula López Martínez, D. Cabello","doi":"10.1109/ASAP.2008.4580175","DOIUrl":"https://doi.org/10.1109/ASAP.2008.4580175","url":null,"abstract":"Modelling of physical phenomena often involves the use of complex systems of equations whose computational solution has demanding requirements in terms of memory and computing power. Among the different techniques proposed, the Finite-Difference Time-Domain (FD-TD) method has the advantage of a feasible hardware implementation that can significantly speed up the computations. This technique is widely used for the solution of partial differential equations in a variety of areas such as antennas design, medical studies, circuit packaging and non-destructive evaluation. In this paper, we present a hardware accelerator of a 3D FD-TD heat equation solver that constitutes the basis of a thermal model of the soil for the non-destructive evaluation of minefields using infrared thermography techniques. In order to be able to work on the field during mine removal activities, a portable and computationally efficient system must be achieved. To this aim, we projected the 3D FD-TD model of the soil onto an FPGA platform using Handel-C and VHDL. A speedup factor of 34 over a single precision PC (C++) is achieved.","PeriodicalId":246715,"journal":{"name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124318388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

A parallel hardware architecture for connected component labeling based on fast label merging 一种基于快速标签合并的连接组件标记并行硬件体系结构

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580169

Holger Flatt, Steffen Blume, Sebastian Hesselbarth, Torsten Schünemann, P. Pirsch

引用次数: 26

A subsampling pulsed UWB demodulator based on a flexible complex SVD 一种基于柔性复奇异值分解的次采样脉冲超宽带解调器

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580164

Y. Vanderperren, W. Dehaene

引用次数: 0

Zodiac: System architecture implementation for a high-performance Network Security Processor 用于高性能网络安全处理器的系统架构实现

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580160

Wang Haixin, Bai Guoqiang, C. Hongyi

引用次数: 12

Accelerating Nussinov RNA secondary structure prediction with systolic arrays on FPGAs 基于fpga的收缩阵列加速Nussinov RNA二级结构预测

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580177

A. Jacob, J. Buhler, R. Chamberlain

引用次数: 40

Floating point multiplication rounding schemes for interval arithmetic 区间算术的浮点乘法舍入方案

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580148

A. Amaricai, M. Vladutiu, M. Udrescu, L. Prodan, O. Boncalo

引用次数: 7

Architecture and VLSI realization of a high-speed programmable decoder for LDPC convolutional codes LDPC卷积码高速可编程解码器的结构与VLSI实现

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580181

M. Tavares, S. Kunze, E. Matús, G. Fettweis

引用次数: 1

Operation shuffling over cycle boundaries for low energy L0 clustering 低能量L0聚类的循环边界操作变换

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580170

Yuki Kobayashi, M. Jayapala, P. Raghavan, F. Catthoor, M. Imai

引用次数: 0