Sundar Balasubramanian, A. Bogdanov, Andy Rupp, Jintai Ding, H. Carter
{"title":"Fast multivariate signature generation in hardware: The case of rainbow","authors":"Sundar Balasubramanian, A. Bogdanov, Andy Rupp, Jintai Ding, H. Carter","doi":"10.1109/FCCM.2008.52","DOIUrl":"https://doi.org/10.1109/FCCM.2008.52","url":null,"abstract":"This paper presents a time-area efficient hardware architecture for the multivariate signature scheme Rainbow. As a part of this architecture, a high-performance hardware optimized variant of the well-known Gaussian elimination over GF(2l) and its efficient implementation are presented. The resulting signature generation core of Rainbow requires 63,593 gate equivalents and signs a message in just 804 clock cycles at 67 MHz using AMI 0.35 mum CMOS technology. Thus, Rainbow provides significant performance improvements compared to RSA and ECDSA.","PeriodicalId":246715,"journal":{"name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124957478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An efficient implementation of a phase unwrapping kernel on reconfigurable hardware","authors":"S. Braganza, M. Leeser","doi":"10.1109/FCCM.2008.56","DOIUrl":"https://doi.org/10.1109/FCCM.2008.56","url":null,"abstract":"The optical quadrature method of microscopy (OQM) uses phase data to capture information about the sample being studied. This phase data need to be unwrapped before it can be of use. Phase unwrapping is the process by which an integer multiple of 2pi is added to a measured, wrapped phase value in order to generate a continuous function. The algorithm used is the minimum LP norm method which uses a two dimensional discrete cosine transform (2-D DCT) which forms the most computationally expensive part of the minimum LP norm method. This paper presents an implementation on reconfigurable hardware that performs the 2-D DCT over the entire 1024 times 512 image, solves the intermediate equation and then performs the two dimensional Inverse discrete cosine transform (2-D IDCT) using a novel FPGA implementation of the DCT with a semi-floating point data representation. This represents the largest 2-D DCT FPGA implementation in the literature, with most previous work focusing on the 8 times 8 transform.","PeriodicalId":246715,"journal":{"name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","volume":"208 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115561673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}