2008 International Conference on Application-Specific Systems, Architectures and Processors最新文献

Rapid estimation of instruction cache hit rates using loop profiling 使用循环分析快速估计指令缓存命中率

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580189

Santanu Kumar Dash, T. Srikanthan

引用次数: 4

Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor AES加密算法在粗粒度可重构阵列处理器上的映射

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580186

Andres Garcia, Mladen Berekovic, T. Aa

引用次数: 17

Novel approach on lifting-based DWT and IDWT processor with multi-context configuration to support different wavelet filters 基于提升的小波变换和多上下文配置的IDWT处理器，以支持不同的小波滤波器

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580195

A. Guntoro, M. Glesner

引用次数: 1

New insights on Ling adders 对凌加德的新见解

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580183

Álvaro Vázquez, E. Antelo

引用次数: 6

Resource efficient generators for the floating-point uniform and exponential distributions 浮点均匀分布和指数分布的资源高效生成器

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580162

David B. Thomas, W. Luk

引用次数: 10

Fault-tolerant dynamically reconfigurable NoC-based SoC 容错动态可重构的基于noc的SoC

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580150

Mohammad Hosseinabady, J. Núñez-Yáñez

引用次数: 18

RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router RECONNECT:使用低开销单周期路由器的多态asic的NoC

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580187

Joseph Nimmy, C. R. Reddy, Keshavan Varadarajan, M. Alle, Alexander Fell, S. Nandy, R. Narayan

{"title":"RECONNECT: A NoC for polymorphic ASICs using a low overhead single cycle router","authors":"Joseph Nimmy, C. R. Reddy, Keshavan Varadarajan, M. Alle, Alexander Fell, S. Nandy, R. Narayan","doi":"10.1109/ASAP.2008.4580187","DOIUrl":"https://doi.org/10.1109/ASAP.2008.4580187","url":null,"abstract":"A polymorphic ASIC is a runtime reconfigurable hardware substrate comprising compute and communication elements. It is a ldquofuture proofrdquo custom hardware solution for multiple applications and their derivatives in a domain. Interoperability between application derivatives at runtime is achieved through hardware reconfiguration. In this paper we present the design of a single cycle Network on Chip (NoC) router that is responsible for effecting runtime reconfiguration of the hardware substrate. The router design is optimized to avoid FIFO buffers at the input port and loop back at output crossbar. It provides virtual channels to emulate a non-blocking network and supports a simple X-Y relative addressing scheme to limit the control overhead to 9 bits per packet. The 8times8 honeycomb NoC (RECONNECT) implemented in 130 nm UMC CMOS standard cell library operates at 500 MHz and has a bisection bandwidth of 28.5 GBps. The network is characterized for random, self-similar and application specific traffic patterns that model the execution of multimedia and DSP kernels with varying network loads and virtual channels. Our implementation with 4 virtual channels has an average network latency of 24 clock cycles and throughput of 62.5% of the network capacity for random traffic. For application specific traffic the latency is 6 clock cycles and throughput is 87% of the network capacity.","PeriodicalId":246715,"journal":{"name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","volume":"2012 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127393301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 19

Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms 扩展SIMPPL SoC架构框架，以支持多fpga平台上的特定应用架构

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580156

David Dickin, Lesley Shannon

{"title":"Extending the SIMPPL SoC architectural framework to support application-specific architectures on multi-FPGA platforms","authors":"David Dickin, Lesley Shannon","doi":"10.1109/ASAP.2008.4580156","DOIUrl":"https://doi.org/10.1109/ASAP.2008.4580156","url":null,"abstract":"Process technology has reduced in size such that it is possible to implement complete application-specific architectures as systems-on-chip (SoCs) using both application-specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). However, the reconfigurable nature of an FPGA results in lower logic density, such that large, complex applications require multi-FPGA implementation platforms. Although designing SoCs is challenging, SoC models such as systems integrating modules with predefined physical links (SIMPPL) exist to facilitate the design process. SIMPPL leverages defined physical interfaces and communication protocols to enable rapid system-level integration for application-specific architectures. This paper presents a ldquoSIMPPL repeaterrdquo that enables the SIMPPL SoC architectural framework to be used for systems spanning multiple FPGAs. The SIMPPL repeater abstracts inter-chip communication, allowing designers to treat a multi-FPGA platform as a single large reconfigurable fabric and focus on their application-specific architecture.","PeriodicalId":246715,"journal":{"name":"2008 International Conference on Application-Specific Systems, Architectures and Processors","volume":"14 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-07-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130059712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Integer and floating-point constant multipliers for FPGAs 用于fpga的整数和浮点常数乘法器

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580184

N. Brisebarre, F. D. Dinechin, J. Muller

引用次数: 35

Fully-pipelined efficient architectures for FPGA realization of discrete Hadamard transform FPGA实现离散Hadamard变换的全流水线高效架构

2008 International Conference on Application-Specific Systems, Architectures and Processors Pub Date : 2008-07-02 DOI: 10.1109/ASAP.2008.4580152

P. Meher, J. Patra

引用次数: 20