Mapping of the AES cryptographic algorithm on a Coarse-Grain reconfigurable array processor

Andres Garcia, Mladen Berekovic, T. Aa
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引用次数: 17

Abstract

Coarse-Grained reconfigurable architectures are emerging as potential candidates to meet the high performance, power efficiency and flexibility needed by embedded systems. ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its DRESC compiler offer a very promising platform for designing embedded systems targeted for different application domains. We present a procedure for mapping the widely used AES cryptographic algorithm on ADRES. A detailed explanation is shown for each of the optimizations performed in order to make better use of instruction and loop parallelism. A new intrinsic function set is proposed for speeding up the processing of the AES algorithm. The obtained simulation results are compared with experiments done on the widely known Texas Instruments DSP: TI C64x, which is considered state-of-the-art for embedded systems. Our results show that ADRES outperforms TI C64x DSP, executing the AES algorithm in one fourth of the cycles.
AES加密算法在粗粒度可重构阵列处理器上的映射
粗粒度可重构架构正在成为满足嵌入式系统所需的高性能、能效和灵活性的潜在候选。动态可重构嵌入式系统体系结构(ADRES)及其DRESC编译器为设计针对不同应用领域的嵌入式系统提供了一个非常有前途的平台。我们提出了一个将广泛使用的AES加密算法映射到地址的程序。为了更好地利用指令和循环的并行性,将对所执行的每项优化进行详细的解释。为了提高AES算法的处理速度,提出了一种新的内禀函数集。所获得的仿真结果与在著名的德州仪器DSP: TI C64x上所做的实验进行了比较,该DSP被认为是嵌入式系统的最新技术。我们的结果表明,ADRES优于TI C64x DSP,在四分之一的周期内执行AES算法。
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