9th International Symposium on Quality Electronic Design (isqed 2008)最新文献_第8页

Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping 一阶参数化攻击者分组统计串扰噪声分析

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.20

Sachin Shrivastava, H. Parameswaran

{"title":"Statistical Crosstalk Noise Analysis Using First Order Parameterized Approach for Aggressor Grouping","authors":"Sachin Shrivastava, H. Parameswaran","doi":"10.1109/ISQED.2008.20","DOIUrl":"https://doi.org/10.1109/ISQED.2008.20","url":null,"abstract":"With decreasing process nodes and increasing design density, crosstalk analysis is a must for getting design closure in the UDSM era. In addition to this, while crosstalk analysis is complex in itself, the new process nodes are showing increasing variations of process parameters for devices and interconnect. This in turn adds more complexity to crosstalk analysis. Standard techniques of factoring in the effects of process variations (corner-based analysis) is particularly ineffective for crosstalk analysis, so we need to look at techniques of statistical analysis of crosstalk in a manner similar to that used for timing. We look at a basic infrastructure for doing statistical crosstalk analysis - and look at how it can incorporate the effects of variations in cell variations and on aggressor slew. We also look at aggressor window clustering as a technique to reduce pessimism in crosstalk - and see how this technique can be modified to take in the effect of process variations. We lay the theoretical framework for these techniques in this paper, and show the results of a prototype implementation on real designs. We show that using this framework and techniques shows a close correlation with Monte-Carlo simulations.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"23 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120965407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

A Low-Power Double-Edge-Triggered Address Pointer Circuit for FIFO Memory Design 一种用于FIFO存储器设计的低功耗双边沿触发地址指针电路

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.129

Saravanan Ramamoorthy, Haibo Wang, S. Vrudhula

引用次数: 0

Process Variation Aware Timing Optimization through Transistor Sizing in Dynamic CMOS Logic 动态CMOS逻辑中晶体管尺寸的工艺变化感知时序优化

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.157

K. Yelamarthi, C. Chen

引用次数: 8

Practical Clock Tree Robustness Signoff Metrics 实用时钟树鲁棒性签名指标

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.171

A. Rajaram, R. Damodaran, A. Rajagopal

{"title":"Practical Clock Tree Robustness Signoff Metrics","authors":"A. Rajaram, R. Damodaran, A. Rajagopal","doi":"10.1109/ISQED.2008.171","DOIUrl":"https://doi.org/10.1109/ISQED.2008.171","url":null,"abstract":"Clock tree analysis and signoff is a key step in the design of any high performance chip. Though simple and intutive metrics like skew have been used to track clock tree quality, they are not sufficient for most practical purposes. Ideally, skew distribution obtained using a SSTA (Statististical Static Timing Analysis) on the clock trees can be used. But in most practical cases, the process information assumed by SSTA is not available. As a result, the signoff of clock skew robustness to variation effects is an often difficult problem to solve. In this work, we propose two metrics that can address this issue. These metrics can be used in three important ways. First, they can be used to determine during CTS whether the clock tree is good enough to go through rest of the backend flow or whether more tuning needs to be done to the clock tree. Second, they can be used to isolate any parts of the clock tree that behaves like a hot spot for clock skew across corners. Third, it can be used as a final signoff metric for clock tree to ensure that the tracking of the delays and skews can be expected to be good across all process points. We provide several experimental results from industry testcases demonstrating the utility of our metrics.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129822660","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects 基于过程变化感知的VLSI互连延迟最小化总线编码方案

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.121

C. Raghunandan, K. S. Sainarayanan, M. Srinivas

引用次数: 4

Fast Evaluation Method for Transient Hot Spots in VLSI ICs in Packages 封装中超大规模集成电路瞬态热点快速评估方法

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.95

Je-Hyoung Park, A. Shakouri, S. Kang

引用次数: 12

Hierarchical Soft Error Estimation Tool (HSEET) 分层软误差估计工具

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.164

K. Ramakrishnan, R. Rajaraman, N. Vijaykrishnan, Yuan Xie, M. J. Irwin, K. Unlu

引用次数: 23

Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses 互连信号和布局优化，以管理由于片上信号总线自加热的热效应

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.101

Krishnan Sundaresan, N. Mahapatra

{"title":"Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses","authors":"Krishnan Sundaresan, N. Mahapatra","doi":"10.1109/ISQED.2008.101","DOIUrl":"https://doi.org/10.1109/ISQED.2008.101","url":null,"abstract":"Power dissipation in long interconnects and increasing wire temperatures due to (self) Joule heating are becoming important issues to address in nanometer-scale technologies. While many low-power bus encoding schemes have been proposed, no encoding techniques exist for explicitly reducing temperatures in high-speed on-chip signal buses. In this work, we propose: (1) an interconnect/wire signaling and layout optimization that considers self and inter-wire coupling activities and is tailored to data traffic characteristics; (2) an integer linear programming (ILP) technique to optimize bus energy and; (3) a novel methodology to add thermal constraints to this ILP optimization to reduce not only average but also peak wire temperatures. Our contributions enable a designer to efficiently explore the hottest wire temperature and total bus dynamic energy trade-off space. One such trade-off point yielded a thermally-constrained, energy-optimal encoding scheme that reduced wire temperatures by up to 12.26degC (12.96degC) for data (instruction) buses and significant average energy savings of 14.24% (16.17%) for data (instruction) bus. These results are still much better than energy reductions obtained by previous work.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121846560","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Interval Based X-Masking for Scan Compression Architectures 扫描压缩架构中基于间隔的x屏蔽

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.31

A. Chandra, R. Kapur

引用次数: 7

Analytical Model for the Propagation Delay of Through Silicon Vias 硅通孔传输延迟的解析模型

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.128

D. Khalil, Y. Ismail, M. Khellah, T. Karnik, V. De

引用次数: 56