9th International Symposium on Quality Electronic Design (isqed 2008)最新文献_第6页

Elastic Timing Scheme for Energy-Efficient and Robust Performance 节能和鲁棒性能的弹性定时方案

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.82

Rupak Samanta, G. Venkataraman, N. Shah, Jiang Hu

{"title":"Elastic Timing Scheme for Energy-Efficient and Robust Performance","authors":"Rupak Samanta, G. Venkataraman, N. Shah, Jiang Hu","doi":"10.1109/ISQED.2008.82","DOIUrl":"https://doi.org/10.1109/ISQED.2008.82","url":null,"abstract":"In nanometer regime, IC designers are struggling between significant variation effects and tight power constraints. The conventional approach - using timing safety margin, consumes power continuously to guard against low probability timing variations. Such power inefficiency is largely eliminated in the Razor technology which detects and corrects variation induced timing errors at runtime. However, the error correction scheme of Razor causes pipeline stalling/flushing and therefore is not preferred in real-time systems or sequential circuits with feedback loops. We propose an elastic timing scheme which can correct timing errors without stalling/flushing pipeline. This is achieved by dynamically boosting circuit speed when timing error occurs. A dynamic clock skew shifting technique is suggested to reduce the boosting cost. An optimization algorithm is also provided to minimize the cost overhead. Compared to conventional safety margin based approach, the elastic timing scheme can reduce power dissipation by 20 % - 27 % on ISCAS89 sequential circuits while retaining similar variation tolerance. After optimization, the boosting is needed for only a small portion of entire circuit. As a result, the area overhead is usually less than 5 %.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126795864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 15

Architecting for Physical Verification Performance and Scaling 架构的物理验证性能和可扩展性

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.109

J. Ferguson, R. Todd

引用次数: 0

System Verilog for Quality of Results (QoR) 结果质量(QoR)系统检验日志

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.52

Ravi Surepeddi

{"title":"System Verilog for Quality of Results (QoR)","authors":"Ravi Surepeddi","doi":"10.1109/ISQED.2008.52","DOIUrl":"https://doi.org/10.1109/ISQED.2008.52","url":null,"abstract":"Design complexity is ever increasing with multi- mode, statistical timing analysis, multi-vt/VDD low power and multi-core performance based type of designs. IEEE 1800 system verilog (Ref 1) is a natural smooth transition language to verilog (Refi and 3) for system level design and verification. Verilog RTL has been popularly used for many design tape outs. System verilog (SV) extensive support exists in verification tools viz. simulators, formal for various powerful SV specific design constructs. It is envisaged that SV will be used for design tape outs soon as many design houses started using SV specific RTL constructs for system designs involving high levels of design data abstractions for various design application keeping in view of verification support. This paper analyzes on various SV design specific constructs for design quality of results (QOR) improvement. The specific constructs discussed for design QOR improvements are 1) operator overloading using user defined types to bring in efficient implementation of data path operators like multiplier, adder, shift,.. 2) Parameterized module interface for different sized datapath, memory, fifo, register files.. 3) Configuration to bind a particular efficient architecture to a module based on QOR requirement 4) System level modules interface and arbitration using \"interface\"construct. 5) Multiple clock domain definition and interface. 6) IEEE1801 UPF low power design intent flow.","PeriodicalId":243121,"journal":{"name":"9th International Symposium on Quality Electronic Design (isqed 2008)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127129369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering 基于fpga的集成电路的重排序晶体管网络合成加速研究

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.168

T. Cardoso, L. Rosa, F. Marques, R. Ribas, A. Reis

引用次数: 3

Finite-Point Gate Model for Fast Timing and Power Analysis 用于快速定时和功率分析的有限点门模型

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.17

Dinesh Ganesan, A. Mitev, Janet Roveda, Yu Cao

引用次数: 5

SEU Vulnerability of Multiprocessor Systems and Task Scheduling for Heterogeneous Multiprocessor Systems 多处理器系统的SEU漏洞及异构多处理器系统的任务调度

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.126

M. Sugihara

引用次数: 8

Tutorial 4: Robust System Design in Scaled CMOS 教程4:缩放CMOS的鲁棒系统设计

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.175

S. Mitra

引用次数: 0

Minimum Shield Insertion on Full-Chip RLC Crosstalk Budgeting Routing 全片RLC串扰预算路由的最小屏蔽插入

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.88

Peng-Yang Hung, Ying-Shu Lou, Yih-Lang Li

引用次数: 1

Error-Tolerant SRAM Design for Ultra-Low Power Standby Operation 超低功耗待机容错SRAM设计

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.38

H. Qin, Animesh Kumar, K. Ramchandran, J. Rabaey, P. Ishwar

引用次数: 13

On the Feasibility of Obtaining a Globally Optimal Floorplanning for an L-shaped Layout Problem l型布局问题全局最优平面规划的可行性研究

9th International Symposium on Quality Electronic Design (isqed 2008) Pub Date : 2008-03-17 DOI: 10.1109/ISQED.2008.27

T. Chang, Manish Kumar, Teng-Sheng Moh, C. Tseng

引用次数: 0