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Digest of Technical Papers., 1990 Symposium on VLSI Circuits最新文献

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A 12.8-MHz sigma-delta modulator with 16-bit performance 具有16位性能的12.8 mhz σ - δ调制器
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111078
B. Brandt, D. Wingard, B. Wooley
{"title":"A 12.8-MHz sigma-delta modulator with 16-bit performance","authors":"B. Brandt, D. Wingard, B. Wooley","doi":"10.1109/VLSIC.1990.111078","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111078","url":null,"abstract":"The authors describe a CMOS second-order Σ-Δ modulator that does not require error correction or component trimming to achieve virtually ideal 16-b performance at a conversion rate of 50 kHz. This modulator is a fully differential circuit that operates from a single 5-V power supply and does not require the use of precision sample-and-hold circuitry. With an oversampling ratio of 256 and a clock rate of 12.8 MHz, an experimental implementation of the modulator achieves a 98-dB dynamic range and 94-dB linearity. The nearly ideal 16-b performance of the modulator and its small area of 0.39 mm2 and power dissipation of only 13.8 mW make it suitable for use as a digital-audio quality analog interface within digital signal processing chips and systems","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134374136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Non-refreshing dynamic RAM for on-chip cache memories 用于片上缓存存储器的非刷新动态RAM
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111120
D.D. Lee, R. Katz
{"title":"Non-refreshing dynamic RAM for on-chip cache memories","authors":"D.D. Lee, R. Katz","doi":"10.1109/VLSIC.1990.111120","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111120","url":null,"abstract":"It is shown that, by using simple circuit techniques and a few modifications to cache organization, one can effectively eliminate the refreshing requirement of a DRAM. A selective invalidation scheme is employed. Selective invalidation can be implemented with a small (six transistors per subblock) circuit. The performances of the DRAM cache with selective invalidation and an equivalent SRAM cache are compared. The difference in performance is quite small even for large caches using selective invalidation. By replacing the SRAM cache with higher-density DRAM, the area efficiency and overall processor performance can be greatly improved. The miss ratio difference in large caches indicates that there are some cache entries active at intervals greater than the refresh period. This may depend on the referencing behavior of program or data","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128987718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A divided/shared bitline sensing scheme for 64 Mb DRAM core 一种用于64mb DRAM内核的分割/共享位线传感方案
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111075
H. Hidaka, Y. Matsuda, K. Fujishima
{"title":"A divided/shared bitline sensing scheme for 64 Mb DRAM core","authors":"H. Hidaka, Y. Matsuda, K. Fujishima","doi":"10.1109/VLSIC.1990.111075","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111075","url":null,"abstract":"New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114537838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture 采用分位线结构的eprom和闪存eeeprom的高速页模式传感方案
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111113
Y. Terada, T. Nakayama, K. Kobayashi, M. Hayashikoshi, S. Kobayashi, Y. Miyawaki, N. Ajika, T. Yoshihara
{"title":"High speed page mode sensing scheme for EPROMs and flash EEEPROMs using divided bit line architecture","authors":"Y. Terada, T. Nakayama, K. Kobayashi, M. Hayashikoshi, S. Kobayashi, Y. Miyawaki, N. Ajika, T. Yoshihara","doi":"10.1109/VLSIC.1990.111113","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111113","url":null,"abstract":"A novel high-speed page mode sense scheme for EPROMs and flash EEPROMs has been developed. A divided bit line architecture makes it possible to adopt a folded bit line architecture in which sense amplifiers are located at the end of the bit lines. Dynamic sensing avoids the soft write problem by reducing bit line voltage and the current flow through the memory cell. An experimental 1-Mb flash EEPROM using a 0.6-μm design rule has been designed. Simulated results show that a high-speed address access time of 60 ns and a page mode access time of 15 ns can be achieved","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114708711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A proposed structure of a 4 Mbit content-addressable and sorting memory 提出了一种4mbit内容可寻址和排序存储器的结构
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111119
I. Okabayashi, H. Kotani, H. Kadota
{"title":"A proposed structure of a 4 Mbit content-addressable and sorting memory","authors":"I. Okabayashi, H. Kotani, H. Kadota","doi":"10.1109/VLSIC.1990.111119","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111119","url":null,"abstract":"A new structure for a high-density 4-Mb CAM (content addressable memory) with sorting function (sort-CAM) is proposed. Retrieval or sorting operations are done in word-parallel/bit-serial manner at the device. This is different from previous CAMs where operations are done in word-parallel/bit-parallel or flash manner. The device organization, circuits for retrieval or sorting, and chip operations are explained. Estimated performance of the device and chip size are also discussed. The device has 64 K-word×64-b organization and a 3.1-MB/s sorting speed. In practical applications, such as RDB (relational database) systems, this speed is enough, but a number of chips should be connected if larger data volume is needed","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127594247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Ultra high sensitivity on-chip amplifier for VLSI CCD image sensor 用于超大规模集成电路CCD图像传感器的超高灵敏度片上放大器
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111094
Y. Matsunaga, H. Yamashita, S. Ohsawa, N. Harada
{"title":"Ultra high sensitivity on-chip amplifier for VLSI CCD image sensor","authors":"Y. Matsunaga, H. Yamashita, S. Ohsawa, N. Harada","doi":"10.1109/VLSIC.1990.111094","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111094","url":null,"abstract":"A novel high-sensitivity on-chip amplifier for CCD (charge coupled device) image sensors is evaluated within a very small signal range of under 20 electrons, which is the photon counting region for highly sensitive imaging devices. Because the output noise of 0.084 mV RMS is smaller than the output voltage/electron of 0.22 mV/electron measured in the larger-signal region, the discrete voltage levels corresponding to numbers of signal electrons were directly observed in an oscilloscope in the small signal region. By this observation, it was confirmed that high responsivity is maintained in the very-small-signal region. Therefore, it is possible to realize a photon-counting solid-state image sensor and a highly sensitive megapixel-level HDTV (high-definition television) imager","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122741407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Pipelined, time-sharing access technique for a highly integrated multi-port memory 一个高度集成的多端口存储器的流水线，分时访问技术
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111118
T. Matsumura, K. Endo, J. Yamada
{"title":"Pipelined, time-sharing access technique for a highly integrated multi-port memory","authors":"T. Matsumura, K. Endo, J. Yamada","doi":"10.1109/VLSIC.1990.111118","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111118","url":null,"abstract":"A pipelined, time-sharing access (PTA) technique that enables a two-port memory cell to operate as a four-port memory cell is proposed. The effectiveness of this technique has been demonstrated by fabricating a 64-kb four-port (read/write) memory with 60-MHz operation under a 3-V supply voltage","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123793060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A 6.8 ns 1 Mb ECL I/O BiCMOS configurable SRAM 一个6.8 ns 1 Mb ECL I/O BiCMOS可配置SRAM
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111084
B. Kertis, G. Costakis, J. Jensen, J. Zeiter, J. Rickard, M. Pusztai, T. Bowman
{"title":"A 6.8 ns 1 Mb ECL I/O BiCMOS configurable SRAM","authors":"B. Kertis, G. Costakis, J. Jensen, J. Zeiter, J. Rickard, M. Pusztai, T. Bowman","doi":"10.1109/VLSIC.1990.111084","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111084","url":null,"abstract":"A 1-Mb ECL (emitter coupled logic) I/O SRAM which has been fabricated using 0.8-μm BiCMOS technology is described. The die is configurable to four different organizations (1 Mb×1, 1 Mb×1 with differential output, 512 K×2 with differential output, and 256 K×4) by way of bonding options. The device, with a die size of 240 mil×475 mil, has a typical access time of 6.8 ns and is 10 K or 100 K I/O compatible with a metal option","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131872755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
VLSI circuit challenges for integrated sensing systems 集成传感系统对VLSI电路的挑战
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111130
K. Wise
{"title":"VLSI circuit challenges for integrated sensing systems","authors":"K. Wise","doi":"10.1109/VLSIC.1990.111130","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111130","url":null,"abstract":"The challenges facing the development of monolithic instrumentation systems are reviewed. Sensor technology is discussed, and examples of merging transducer and circuit processes are given. It is noted that, for many future systems, transducers, analog circuits, logic, and memory should probably be merged on a single chip, and system-level standards are needed to focus such efforts. It is concluded that microcomputer-based sensing nodes capable of functioning as smart peripherals and employing features such as self-testing, autocalibration, and PROM-based digital compensation should be realizable on a single chip within a decade","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134025942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Environment and methodology for accurate noise simulation of VLSI circuits VLSI电路精确噪声模拟的环境与方法
Digest of Technical Papers., 1990 Symposium on VLSI Circuits Pub Date : 1990-06-07 DOI: 10.1109/VLSIC.1990.111106
M. Marlett, B. Prickett, R. Lall, N. Chidambaram
{"title":"Environment and methodology for accurate noise simulation of VLSI circuits","authors":"M. Marlett, B. Prickett, R. Lall, N. Chidambaram","doi":"10.1109/VLSIC.1990.111106","DOIUrl":"https://doi.org/10.1109/VLSIC.1990.111106","url":null,"abstract":"An integrated simulation environment which accurately models the noise behavior of VLSI circuits in a package with reasonable simulation time has been developed. These models are generated by automatic tools developed for this purpose. When used in a methodical approach to noise analysis, the tools speed up the simulation process and make it possible to reliably predict the behavior of a VLSI circuit in a package before it is fabricated. Theoretical package-pin models have been correlated with scattering parameter measurements, SPICE simulations, electrical-parameter simulation, and bench measurements. Die parasitics are automatically extracted to produce a compact die model. Models for the package-pins, the die capacitance, the active circuits, and the output loads are combined to simulate the noise behavior of a circuit","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132129151","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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