A proposed structure of a 4 Mbit content-addressable and sorting memory

Abstract

A new structure for a high-density 4-Mb CAM (content addressable memory) with sorting function (sort-CAM) is proposed. Retrieval or sorting operations are done in word-parallel/bit-serial manner at the device. This is different from previous CAMs where operations are done in word-parallel/bit-parallel or flash manner. The device organization, circuits for retrieval or sorting, and chip operations are explained. Estimated performance of the device and chip size are also discussed. The device has 64 K-word×64-b organization and a 3.1-MB/s sorting speed. In practical applications, such as RDB (relational database) systems, this speed is enough, but a number of chips should be connected if larger data volume is needed