{"title":"一种用于64mb DRAM内核的分割/共享位线传感方案","authors":"H. Hidaka, Y. Matsuda, K. Fujishima","doi":"10.1109/VLSIC.1990.111075","DOIUrl":null,"url":null,"abstract":"New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond","PeriodicalId":239990,"journal":{"name":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","volume":"106 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-06-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A divided/shared bitline sensing scheme for 64 Mb DRAM core\",\"authors\":\"H. Hidaka, Y. Matsuda, K. Fujishima\",\"doi\":\"10.1109/VLSIC.1990.111075\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond\",\"PeriodicalId\":239990,\"journal\":{\"name\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"volume\":\"106 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-06-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers., 1990 Symposium on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1990.111075\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers., 1990 Symposium on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1990.111075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A divided/shared bitline sensing scheme for 64 Mb DRAM core
New high-density DRAM core designs based on a new divided bitline sensing principle are proposed and their performance is estimated. These designs can achieve a high-density memory cell array and can also overcome problems of the scaled memory array. These designs are promising candidates for 64-Mb DRAM and beyond
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