{"title":"Response Time Analysis with Limited Carry-In for Global Earliest Deadline First Scheduling","authors":"Youcheng Sun, G. Lipari","doi":"10.1109/RTSS.2015.20","DOIUrl":"https://doi.org/10.1109/RTSS.2015.20","url":null,"abstract":"We address the problem of schedulability analysis for a set of sporadic real-time tasks scheduled by the Global Earliest Deadline First (G-EDF) policy on a multiprocessor platform. State-of-the-art tests for schedulability analysis of multiprocessor global scheduling are often incomparable. That is, a task set that is judged not schedulable by a test may be verified to be schedulable by another test, and vice versa. In this paper, we first develop a new schedulability test that integrates the limited carry-in technique and Response Time Analysis (RTA) procedure for Global EDF schedulability analysis. Then, we provide an over-approximate variant of this test with better run-time efficiency. Later, we extend these two tests to self-suspending tasks. All schedulability tests proposed in the paper have provable dominance over their state-of-the-art counterparts. Finally, we conduct extensive comparisons among different schedulability tests. Our new tests show significant improvements for schedulability analysis of Global EDF.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124002229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yi Zhang, Jiliang Wang, Yuan He, Yanrong Kang, Bo Li, Yunhao Liu
{"title":"Q-Offload: Quality Aware WiFi Offloading with Link Dynamics","authors":"Yi Zhang, Jiliang Wang, Yuan He, Yanrong Kang, Bo Li, Yunhao Liu","doi":"10.1109/RTSS.2015.30","DOIUrl":"https://doi.org/10.1109/RTSS.2015.30","url":null,"abstract":"Driven by the proliferation of mobile applications, the conflict between data communication requirement and limited battery capacity is becoming sharp on modern smartphones. Offloading mobile traffic from cellular to WiFi is widely recognized as a viable solution to improve the energy efficiency. However, through extensive field experiments, we find WiFi offloading is not always energy efficient and even consumes more energy than cellular network due to link quality variation. In addition, we also observe that practical data transmission deadline requirement and link utilization allows scheduling of data traffic to time periods with good link quality. Accordingly, we propose Q-offload, the first attempt towards energy efficient WiFi offloading with link dynamics. In Q-offload, we propose an iterative framework to achieve energy efficient WiFi offloading by exploiting good link quality while not affecting user experience. We evaluate the performance of Q-offload through both trace-driven analysis and real-world experiments. The results show that it can achieve 33.5%~55.7% energy efficiency improvement, compared with state-of-the-arts under different conditions.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"320 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121350887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Maolin Yang, Alexander Wieder, Björn B. Brandenburg
{"title":"Global Real-Time Semaphore Protocols: A Survey, Unified Analysis, and Comparison","authors":"Maolin Yang, Alexander Wieder, Björn B. Brandenburg","doi":"10.1109/RTSS.2015.8","DOIUrl":"https://doi.org/10.1109/RTSS.2015.8","url":null,"abstract":"All major real-time suspension-based locking protocols (or semaphore protocols) for global fixed-priority scheduling are reviewed and a new, unified response-time analysis framework applicable to all protocols is proposed. The newly proposed analysis, based on linear programming, is shown to be clearly preferable compared to all prior conventional approaches. Based on the new analysis, all protocols are directly compared with each other in a large-scale schedulability study. Interestingly, the Priority Inheritance Protocol (PIP) and the Flexible Multiprocessor Locking Protocol (FMLP), which are the two oldest and simplest of the considered protocols, are found to perform best.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134543106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved DRAM Timing Bounds for Real-Time DRAM Controllers with Read/Write Bundling","authors":"L. Ecco, R. Ernst","doi":"10.1109/RTSS.2015.13","DOIUrl":"https://doi.org/10.1109/RTSS.2015.13","url":null,"abstract":"As DRAMs become faster, the penalty to reverse the direction of their data buses increases. Yet, existing real-time memory controllers do not reorder read and write commands. Hence, timing bounds are computed by assuming an alternating pattern of reads and writes, thus accounting for several data bus direction reversals, consequently leading to suboptimal results. Therefore, in this paper, we propose a memory controller that reorders read and write commands, which minimizes reversals. Moreover, we prove through a detailed timing analysis that the effect of the reordering is bounded. Finally, we compare our approach analytically with a state-of-the-art real-time memory controller and show that our timing bounds are up to 27% better.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126381127","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Time-Predictable Model of Computation","authors":"Anoop Bhagyanath, Tripti Jain, K. Schneider","doi":"10.1109/RTSS.2015.45","DOIUrl":"https://doi.org/10.1109/RTSS.2015.45","url":null,"abstract":"Effectiveness of timing analysis of real-time applications depends on the timing predictability of the underlying execution platform. Modern hardware architectures improve average case performance using complex features. However, these features make Worst Case Execution Time (WCET) analysis complicated often leading to pessimistic derived worst case execution time. We present the preliminary design of Synchronous Control Asynchronous Dataflow (SCAD) - a new model of computation targeting time-predictability and competitive performance. Inorder execution of instructions and capability to bypass memory accesses imparts timing predictability to SCAD computational model. We also motivate a code generation technique to optimally utilize the memory bypassing capability of SCAD and that results in increased instruction level parallelism.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128302961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reducing the Implementation Overheads of IPCP and DFP","authors":"H. Almatary, N. Audsley, A. Burns","doi":"10.1109/RTSS.2015.35","DOIUrl":"https://doi.org/10.1109/RTSS.2015.35","url":null,"abstract":"Most resource control protocols such as IPCP (Immediate Priority Ceiling Protocol) require a kernel system call to implement the necessary control over any shared data. This call can be expensive, involving a potentially slow switch from CPU user-mode to kernel-mode (and back). In this paper we look at two anticipatory schemes (IPCP and DFP - Deadline Floor Protocol) and show how they can be implemented with the minimum number of calls on the kernel. Specifically, no kernel calls are needed when there is no contention, and only one when there is. A standard implementation would need two such calls. The protocols developed are verified by the use of model checking. A prototype implementation is described for POSIX pThreads (thus opening up improvements to a range of programming approaches). Experimental results demonstrate the effectiveness of the scheme, showing average case savings of 86%.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122729252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Micaiah Chisholm, Bryan C. Ward, Namhoon Kim, James H. Anderson
{"title":"Cache Sharing and Isolation Tradeoffs in Multicore Mixed-Criticality Systems","authors":"Micaiah Chisholm, Bryan C. Ward, Namhoon Kim, James H. Anderson","doi":"10.1109/RTSS.2015.36","DOIUrl":"https://doi.org/10.1109/RTSS.2015.36","url":null,"abstract":"In mixed-critical applications, tension exists between sharing and isolation with respect to hardware resources: while strong isolation might be required for highly critical tasks, somewhat permissive sharing might be reasonable for less critical tasks to improve throughput or average-case performance. In this paper, this tension is examined as it pertains to shared last-level caches (LLCs) on multicore platforms. In particular, criticality-aware optimization techniques based on linear programming are presented for allocating LLC areas in the context of the previously proposed MC2 (mixed-criticality on multicore) framework. Experiments are also presented that show that these techniques can result in significant schedulability improvements.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"23 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129666097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. NischalK., Paritosh Kelkar, D. Kumar, Y. Pant, Houssam Abbas, Joseph Devietti, R. Mangharam
{"title":"Hardware Optimizations for Anytime Perception and Control","authors":"N. NischalK., Paritosh Kelkar, D. Kumar, Y. Pant, Houssam Abbas, Joseph Devietti, R. Mangharam","doi":"10.1109/RTSS.2015.49","DOIUrl":"https://doi.org/10.1109/RTSS.2015.49","url":null,"abstract":"Autonomous vehicles promise significant benefits to society, from reduced accident rates to greater mobility for the elderly. The biggest challenge in the design of autonomous vehicles comes from the uncertainty of the environment in which they will operate. Their control algorithms must be able to cope with driving events that occur on widely ranging time scales. For example, relaxed rural driving can accommodate planning actions every few seconds, while imminent collision avoidance requires planning and actuation on the order of a few milliseconds. Thus 'real-time' performance will imply different things depending on the context.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116398530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pei-Chi Huang, L. Sentis, J. Lehman, Chien-Liang Fok, A. Mok, R. Miikkulainen
{"title":"Tradeoffs in Real-Time Robotic Task Design with Neuroevolution Learning for Imprecise Computation","authors":"Pei-Chi Huang, L. Sentis, J. Lehman, Chien-Liang Fok, A. Mok, R. Miikkulainen","doi":"10.1109/RTSS.2015.27","DOIUrl":"https://doi.org/10.1109/RTSS.2015.27","url":null,"abstract":"We present a study on the tradeoffs between three design parameters for robotic task systems that function in partially unknown and unstructured environments, and under timing constraints. The design space of these robotic tasks must incorporate at least three dimensions: (1) the amount of training effort to teach the robot to perform the task, (2) the time available to complete the task from the point when the command is given to perform the task, and (3) the quality of the result from performing the task. This paper presents a tradeoff study in this design space for a common robotic task, specifically, grasping of unknown objects in unstructured environments. The imprecise computation model is used to provide a framework for this study. The results were validated with a real robot and contribute to the development of a systematic approach for designing robotic task systems that must function in environments like flexible manufacturing systems of the future.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128091978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Relaxing Resource-Sharing Constraints for Improved Hardware Management and Schedulability","authors":"Bryan C. Ward","doi":"10.1109/RTSS.2015.22","DOIUrl":"https://doi.org/10.1109/RTSS.2015.22","url":null,"abstract":"Modern computer architectures, particularly multicore systems, include shared hardware resources such as caches and interconnects that introduce timing-interference channels. Unmanaged access to such resources can adversely affect the execution time of other tasks, and lead to unpredictable execution times and associated analysis pessimism that can entirely negate the benefits of a multicore processor. To mitigate such effects, accesses to shared hardware resources should be managed, for example, by a real-time locking protocol. However, accesses to some hardware resources can be managed with more relaxed sharing constraints than mutual exclusion while still mitigating timing-interference channels. This paper presents two new classes of sharing constraints, preemptive mutual exclusion, and half-protected sharing, which are motivated by the sharing constraints of buses and caches, respectively. Synchronization algorithms are presented for both sharing constraints, where applicable, on both uni-and multi-processor systems. A fundamentally new analysis technique called idleness analysis is presented to account for the effects of blocking in globally scheduled multiprocessor systems. Experimental results suggest that these relaxed synchronization requirements and improved analysis techniques can improve schedulability by up to 250%. Furthermore, idleness analysis can be applied to existing locking protocols to improve schedulability in many cases.","PeriodicalId":239882,"journal":{"name":"2015 IEEE Real-Time Systems Symposium","volume":"116 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120873006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}