{"title":"Power gating in asynchronous micropiplines for low power data driven computing","authors":"Austin Ogweno, A. Yakovlev, P. Degenaar","doi":"10.1109/PRIME.2015.7251405","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251405","url":null,"abstract":"In this work we explore the extent at which power gating in asynchronous micropipelines is beneficial at low operating voltages at different input data rates. In addition we present a further improvement to previous techniques by adding the delay blocks to the power gated voltage domains to reduce the leakage energy consumed by these blocks. An asynchronous FIR filter with 4 phase bundled data handshake protocol is presented with and without power shutoff. Implementation is done in 90nm CMOS and simulations performed at 600mV with different input data rates and the total energy consumption recorded. It was noted that at lower data rates, the circuit design with fine grained power gating is energy efficient while at higher data rates it consumes more energy than one without power gating. Our design achieves a total energy saving of 43% at 1KHz input data rate compared to 31% for the previous technique.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115673529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ka-Meng Lei, H. Heidari, Pui-in Mak, M. Law, F. Maloberti
{"title":"Exploring the noise limits of fully-differential micro-watt transimpedance amplifiers for Sub-pA/yHz sensitivity","authors":"Ka-Meng Lei, H. Heidari, Pui-in Mak, M. Law, F. Maloberti","doi":"10.1109/PRIME.2015.7251392","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251392","url":null,"abstract":"This paper explores the noise performance limits of the differential configurations of differential transimpedance amplifiers (TIAs), which serve as a current detection front-end and converts signals for backend signal processing. TIA is one of the most frequent module adopted in biological and environmental sensing such as hall sensors and DNA synthesis detection, which require noise density down to sub-pA/√Hz with micro-watt power consumption so detailed analysis on the noise performance is required. The noises for three different TIAs, including the common-gate topology, op-amp based resistive feedback and capacitive feedback, have been investigated and simulated. Among them, op-amp based capacitive feedback, which bases on integration of input current, displays the lowest noise and best performance. Simulated in 180 nm CMOS process, the capacitive feedback technology shows an input-referred noise of 16 fA/√Hz (80 fA/√Hz) at 10 kHz (100 Hz), featuring it a promising solution for current detection.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121024220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"High efficiency magnetic resonance wireless power transfer system and charging IC for mobile devices","authors":"Jinhwan Youn, J. Choi","doi":"10.1109/PRIME.2015.7251375","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251375","url":null,"abstract":"In this paper, we propose enhanced wireless power transfer system based on magnetic resonance for portable electronic device charging. Resonators are designed and fabricated for efficiency improvement and miniaturization through electromagnetic simulation tools. Impedance matching technique is utilized to improve the transmission power efficiency by modulating the impedance at the transmitter end to match the load impedance. The fabricated receiver IC consists of rectifier, DC-DC converter and charging control circuit designed to reduce the power loss in the power conversion stages. This chip is implemented in 0.35μm BCD technology. A maximum overall efficiency of 73.8% was determined for the system.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126924006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fuzzy-logic based voltage-frequency controller for network-on-chip routers","authors":"Hai-Phong Phan, Xuan-Tu Tran","doi":"10.1109/PRIME.2015.7251367","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251367","url":null,"abstract":"Low power design can be easily achieved by scaling the voltage and frequency of the target systems. The most concerning issue is how to make the voltage-frequency scaling adaptable to the required performance of the system at run-time. In this paper, we present the design of a voltage-frequency controller for network-on-chip routers based on fuzzy-logic processing. The communication traffic of a network router will be predicted by a fuzzy-logic algorithm. Then the voltage and frequency of the router will be scaled according to the predicted results in order to get power consumption optimal for the network router. The most important part of the proposed controller, the fuzzy-logic processor (FLP), is modeled and verified using VHDL and then implemented on FPGA devices.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116457258","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Electromagnetic evaluation of Class-D switching schemes","authors":"Timuçin Karaca, B. Deutschmann","doi":"10.1109/PRIME.2015.7251347","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251347","url":null,"abstract":"Class-D audio amplifiers may significantly contribute to the electromagnetic emissions of electronic devices. This work deals with the electromagnetic emissions created by Class-D amplifier output stages. Output stage switching schemes of traditional and filterless Class-D amplifiers are analyzed concerning their ability to create electromagnetic disturbances. Three different switching schemes are compared, namely Class-AD, Class-BD, and Ternary switching. Finally, commercially available Class-D amplifier ICs are measured and compared using an electromagnetic compatibility measurement setup according to IEC61967-4-A1.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128240025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
F. Santoro, D. Schmitt-Landsiedel, N. Gibson, R. Kuhn, T. Tost, R. Brederlow
{"title":"An ultra-low power, 2mA Iout buck converter optimized for <50mV ripple at a load cap of only 27nF","authors":"F. Santoro, D. Schmitt-Landsiedel, N. Gibson, R. Kuhn, T. Tost, R. Brederlow","doi":"10.1109/PRIME.2015.7251371","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251371","url":null,"abstract":"A novel, simple DC-DC concept for low-power applications is presented. We propose a predictive peak-current mode controller in discontinuous conduction mode (DCM). The design is able to operate with a minimized output capacitor of only 27nF. Measurements shows low ripple voltage even at maximum load current steps and excellent transient response at a good DC control of Vout.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130441905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Communication energy constrained spare core on NoC","authors":"B. N. Kumar, Dheeraj Sharma","doi":"10.1109/PRIME.2015.7251084","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251084","url":null,"abstract":"In Multi-processor System on-chip, each processor produce and consumes high data. Transporting of data is a crucial role in MPSOC, Therefore Network on Chip (NoC) preferred as a communication medium, because good communication performance and fast operating. While considering NoC Architectural some temporary, permanent faults occur in the core. This paper propose the placement of spare core and its communication energy constraints, we investigated energy metrics in place of spare core and finally saving communication energy leads to previous algorithms.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116923882","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast switch bootstrapping for GS/s high-resolution analog-to-digital converter","authors":"A. Ramkaj, F. Tavernier, M. Steyaert","doi":"10.1109/PRIME.2015.7251337","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251337","url":null,"abstract":"This paper presents a novel bootstrapped switch to serve as an input frontend for high resolution ADCs operating in the GHz frequency range. The switch reduces the on-resistance value and keeps it constant, resulting in precise sampling of input signals and better tracking bandwidth. The proposed bootstrapped switch is designed and simulated in TSMC 28 nm Digital CMOS. Simulation results at 800 MSamples/s show an improved and relatively constant spurious-free dynamic range (SFDR) and total harmonic distortion (THD) up to an input frequency of 1.6 GHz, which makes it suitable for a Time-Interleaved configuration.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123669426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Low complexity all-pass based polyphase decimation filters for ECG monitoring","authors":"Yaprak Eminaga, Adem Coskun, S. Moschos, I. Kale","doi":"10.1109/PRIME.2015.7251400","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251400","url":null,"abstract":"This paper presents a low complexity high efficiency decimation filter which can be employed in EletroCardioGram (ECG) acquisition systems. The decimation filter with a decimation ratio of 128 works along with a third order sigma delta modulator. It is designed in four stages to reduce cost and power consumption. The work reported here provides an efficient approach for the decimation process for high resolution biomedical data conversion applications by employing low complexity two-path all-pass based decimation filters. The performance of the proposed decimation chain was validated by using the MIT-BIH arrhythmia database and comparative simulations were conducted with the state of the art.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123987987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finite element analysis of uniaxial bending of ultra-thin silicon dies embedded in flexible foil substrates","authors":"N. Palavesam, C. Landesberger, C. Kutter, K. Bock","doi":"10.1109/PRIME.2015.7251353","DOIUrl":"https://doi.org/10.1109/PRIME.2015.7251353","url":null,"abstract":"We report a Finite Element Model to calculate the bending stress of thin and ultra-thin silicon dies embedded in flexible foil substrates (chip-in-foil package) at lower bending radii. The values of fracture strength computed using Finite Element Analysis showed very good agreement with the experimental results. Furthermore, an increase in the fracture or critical stress (bending stress at fracture) of the dies due to embedding in flexible foil substrates was observed. Besides, the impact of foil material and thickness on the bending stress of ultra-thin silicon die is discussed by comparing two foil materials: Stainless Steel and Polyimide.","PeriodicalId":237786,"journal":{"name":"2015 11th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128549293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}