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International Workshop on Applied Reconfigurable Computing最新文献

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Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems 可重构多加速器系统中提高生产率的自动化工具链
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_4
A. Ortiz, Rafael Zamacola, Alfonso Rodríguez, A. Otero, E. D. L. Torre
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引用次数: 0
Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs 基于Xilinx fpga的资源高效动态电压和频率缩放
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_14
Gökhan Akgün, Lester Kalms, D. Göhringer
{"title":"Resource Efficient Dynamic Voltage and Frequency Scaling on Xilinx FPGAs","authors":"Gökhan Akgün, Lester Kalms, D. Göhringer","doi":"10.1007/978-3-030-44534-8_14","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_14","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131855268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Cross-layer CNN Approximations for Hardware Implementation 硬件实现的跨层CNN近似
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_12
Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, S. Niar
{"title":"Cross-layer CNN Approximations for Hardware Implementation","authors":"Karim M. A. Ali, Ihsen Alouani, Abdessamad Ait El Cadi, Hamza Ouarnoughi, S. Niar","doi":"10.1007/978-3-030-44534-8_12","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_12","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133487960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters 高性能FPGA集群中直接网络和间接网络的比较
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_24
Antoniette Mondigo, Tomohiro Ueno, K. Sano, H. Takizawa
{"title":"Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters","authors":"Antoniette Mondigo, Tomohiro Ueno, K. Sano, H. Takizawa","doi":"10.1007/978-3-030-44534-8_24","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_24","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130263094","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Chisel Usecase: Designing General Matrix Multiply for FPGA 用例:FPGA通用矩阵乘法的设计
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_5
Bruno Ferres, O. Muller, F. Rousseau
{"title":"Chisel Usecase: Designing General Matrix Multiply for FPGA","authors":"Bruno Ferres, O. Muller, F. Rousseau","doi":"10.1007/978-3-030-44534-8_5","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_5","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131876360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment HBM2 FPGA上基于块的收缩阵列用于DNA序列比对
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_23
Riadh Ben Abdelhamid, Y. Yamaguchi
{"title":"A Block-Based Systolic Array on an HBM2 FPGA for DNA Sequence Alignment","authors":"Riadh Ben Abdelhamid, Y. Yamaguchi","doi":"10.1007/978-3-030-44534-8_23","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_23","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"32 1 Pt 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125707995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels 探索fpga优化计算稀疏数值线性代数核
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_20
Federico Favaro, Ernesto Dufrechu, P. Ezzatti, J. Oliver
{"title":"Exploring fpga Optimizations to Compute Sparse Numerical Linear Algebra Kernels","authors":"Federico Favaro, Ernesto Dufrechu, P. Ezzatti, J. Oliver","doi":"10.1007/978-3-030-44534-8_20","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_20","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122888102","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices 硬件任务到可重构计算设备的调度和映射的最优和贪婪启发式方法
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_9
Zakarya Guettatfi, Paul Kaufmann, M. Platzner
{"title":"Optimal and Greedy Heuristic Approaches for Scheduling and Mapping of Hardware Tasks to Reconfigurable Computing Devices","authors":"Zakarya Guettatfi, Paul Kaufmann, M. Platzner","doi":"10.1007/978-3-030-44534-8_9","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_9","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130636975","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks 卷积神经网络高效高级综合的模块化软件库
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_16
Hector Gerardo Muñoz Hernandez, Safdar Mahmood, M. Brandalero, M. Hübner
{"title":"A Modular Software Library for Effective High Level Synthesis of Convolutional Neural Networks","authors":"Hector Gerardo Muñoz Hernandez, Safdar Mahmood, M. Brandalero, M. Hübner","doi":"10.1007/978-3-030-44534-8_16","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_16","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130798624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Technique for Vendor and Device Agnostic Hardware Area-Time Estimation 与厂商和设备无关的硬件区域时间估计技术
International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_13
Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, T. Srikanthan, Thilina Perera
{"title":"Technique for Vendor and Device Agnostic Hardware Area-Time Estimation","authors":"Deshya Wijesundera, Kushagra Shah, Kisaru Liyanage, Alok Prakash, T. Srikanthan, Thilina Perera","doi":"10.1007/978-3-030-44534-8_13","DOIUrl":"https://doi.org/10.1007/978-3-030-44534-8_13","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122913225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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