发布求助
文献互助 智能选刊 最新文献

International Workshop on Applied Reconfigurable Computing最新文献

筛选
英文 中文
Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network 基于人工神经网络的FPGA模块模块化设计方法性能评估
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_9
Kalindu Herath, Alok Prakash, T. Srikanthan
{"title":"Performance Estimation of FPGA Modules for Modular Design Methodology Using Artificial Neural Network","authors":"Kalindu Herath, Alok Prakash, T. Srikanthan","doi":"10.1007/978-3-319-78890-6_9","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_9","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134249821","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic 基于可重构逻辑的低精度神经网络的精度与吞吐量权衡
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_3
Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, P. Leong, P. Cheung
{"title":"Accuracy to Throughput Trade-Offs for Reduced Precision Neural Networks on Reconfigurable Logic","authors":"Jiang Su, Nicholas J. Fraser, Giulio Gambardella, Michaela Blott, Gianluca Durelli, David B. Thomas, P. Leong, P. Cheung","doi":"10.1007/978-3-319-78890-6_3","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_3","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124160136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors 嵌入式处理器侵入式动态可重构周期精确调试系统
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_35
Habib ul Hasan Khan, Ahmed Kamal, D. Göhringer
{"title":"An Intrusive Dynamic Reconfigurable Cycle-Accurate Debugging System for Embedded Processors","authors":"Habib ul Hasan Khan, Ahmed Kamal, D. Göhringer","doi":"10.1007/978-3-319-78890-6_35","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_35","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121452847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads ReneGENE-Novo:共同设计的加速预处理和基因组短读段组装的算法架构
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_45
S. Natarajan, N. K. Kumar, H. V. Anuchan, D. Pal, S. Nandy
{"title":"ReneGENE-Novo: Co-designed Algorithm-Architecture for Accelerated Preprocessing and Assembly of Genomic Short Reads","authors":"S. Natarajan, N. K. Kumar, H. V. Anuchan, D. Pal, S. Nandy","doi":"10.1007/978-3-319-78890-6_45","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_45","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121034616","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Fast DSE for Automated Parallelization of Embedded Legacy Applications 嵌入式遗留应用程序自动并行化的快速DSE
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_38
Kris Heid, Jakob Wenzel, C. Hochberger
{"title":"Fast DSE for Automated Parallelization of Embedded Legacy Applications","authors":"Kris Heid, Jakob Wenzel, C. Hochberger","doi":"10.1007/978-3-319-78890-6_38","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_38","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116749602","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An FPGA/HMC-Based Accelerator for Resolution Proof Checking 一种基于FPGA/ hmc的分辨率校验加速器
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_13
Tim Hansmeier, M. Platzner, D. Andrews
{"title":"An FPGA/HMC-Based Accelerator for Resolution Proof Checking","authors":"Tim Hansmeier, M. Platzner, D. Andrews","doi":"10.1007/978-3-319-78890-6_13","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_13","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121200855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications ARAMiS项目倡议-安全和混合关键应用中的多核系统
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_55
J. Becker, F. Bapp
{"title":"The ARAMiS Project Initiative - Multicore Systems in Safety- and Mixed-Critical Applications","authors":"J. Becker, F. Bapp","doi":"10.1007/978-3-319-78890-6_55","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_55","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126937892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors 软错误下AP-SoC硬件加速的AXI流接口分析
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_20
F. Benevenuti, F. Kastensmidt
{"title":"Analyzing AXI Streaming Interface for Hardware Acceleration in AP-SoC Under Soft Errors","authors":"F. Benevenuti, F. Kastensmidt","doi":"10.1007/978-3-319-78890-6_20","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_20","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125627741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
High Performance UDP/IP 40Gb Ethernet Stack for FPGAs 用于fpga的高性能UDP/IP 40Gb以太网堆栈
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_21
Milind M. Parelkar, Darshan Jetly
{"title":"High Performance UDP/IP 40Gb Ethernet Stack for FPGAs","authors":"Milind M. Parelkar, Darshan Jetly","doi":"10.1007/978-3-319-78890-6_21","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_21","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133988158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs 分析泰勒级数近似在硬件和嵌入式软件中的应用，以实现良好的成本-精度权衡
International Workshop on Applied Reconfigurable Computing Pub Date : 2018-05-02 DOI: 10.1007/978-3-319-78890-6_52
G. Rodrigues, Ádria Barros de Oliveira, F. Kastensmidt, A. Bosio
{"title":"Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs","authors":"G. Rodrigues, Ádria Barros de Oliveira, F. Kastensmidt, A. Bosio","doi":"10.1007/978-3-319-78890-6_52","DOIUrl":"https://doi.org/10.1007/978-3-319-78890-6_52","url":null,"abstract":"","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-05-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134110471","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
首页 上一页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信