International Workshop on Applied Reconfigurable Computing最新文献

Reconfigurable Edge Hardware for Intelligent IDS: Systematic Approach 用于智能 IDS 的可重构边缘硬件：系统方法

International Workshop on Applied Reconfigurable Computing Pub Date : 2024-04-13 DOI: 10.1007/978-3-031-55673-9_4

Wadid Foudhaili, Anouar Nechi, Celine Thermann, Mohammad Al Johmani, R. Buchty, Mladen Berekovic, Saleh Mulhem

引用次数: 0

Implementation of a perception system for autonomous vehicles using a detection-segmentation network in SoC FPGA 在SoC FPGA中使用检测分割网络实现自动驾驶车辆感知系统

International Workshop on Applied Reconfigurable Computing Pub Date : 2023-07-17 DOI: 10.48550/arXiv.2307.08682

Maciej Baczmanski, Mateusz Wasala, T. Kryjak

{"title":"Implementation of a perception system for autonomous vehicles using a detection-segmentation network in SoC FPGA","authors":"Maciej Baczmanski, Mateusz Wasala, T. Kryjak","doi":"10.48550/arXiv.2307.08682","DOIUrl":"https://doi.org/10.48550/arXiv.2307.08682","url":null,"abstract":"Perception and control systems for autonomous vehicles are an active area of scientific and industrial research. These solutions should be characterised by high efficiency in recognising obstacles and other environmental elements in different road conditions, real-time capability, and energy efficiency. Achieving such functionality requires an appropriate algorithm and a suitable computing platform. In this paper, we have used the MultiTaskV3 detection-segmentation network as the basis for a perception system that can perform both functionalities within a single architecture. It was appropriately trained, quantised, and implemented on the AMD Xilinx Kria KV260 Vision AI embedded platform. By using this device, it was possible to parallelise and accelerate the computations. Furthermore, the whole system consumes relatively little power compared to a CPU-based implementation (an average of 5 watts, compared to the minimum of 55 watts for weaker CPUs, and the small size (119mm x 140mm x 36mm) of the platform allows it to be used in devices where the amount of space available is limited. It also achieves an accuracy higher than 97% of the mAP (mean average precision) for object detection and above 90% of the mIoU (mean intersection over union) for image segmentation. The article also details the design of the Mecanum wheel vehicle, which was used to test the proposed solution in a mock-up city.","PeriodicalId":234453,"journal":{"name":"International Workshop on Applied Reconfigurable Computing","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122196864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Implementation of a perception system for autonomous vehicles using a detection-segmentation network in SoC FPGA 利用 SoC FPGA 中的检测-分割网络实现自动驾驶汽车感知系统

International Workshop on Applied Reconfigurable Computing Pub Date : 2023-07-17 DOI: 10.1007/978-3-031-42921-7_14

Maciej Baczmanski, Mateusz Wasala, T. Kryjak

引用次数: 0

FPGA-Extended General Purpose Computer Architecture fpga扩展的通用计算机体系结构

International Workshop on Applied Reconfigurable Computing Pub Date : 2022-03-19 DOI: 10.1007/978-3-031-19983-7_7

Philippos Papaphilippou, Myrtle Shah

引用次数: 1

Fast Approximation of the Top-k Items in Data Streams Using a Reconfigurable Accelerator 使用可重构加速器快速逼近数据流中Top-k项

International Workshop on Applied Reconfigurable Computing Pub Date : 2021-06-29 DOI: 10.1007/978-3-030-79025-7_1

Ali Ebrahim, Jalal Khalifat

引用次数: 1

Accelerating Convolutional Neural Networks in FPGA-based SoCs using a Soft-Core GPU 使用软核GPU加速基于fpga的soc中的卷积神经网络

International Workshop on Applied Reconfigurable Computing Pub Date : 2021-06-29 DOI: 10.1007/978-3-030-79025-7_20

Hector Gerardo Muñoz Hernandez, M. Veleski, M. Brandalero, M. Hübner

引用次数: 2

High-Level Synthesis in Implementing and Benchmarking Number Theoretic Transform in Lattice-Based Post-Quantum Cryptography Using Software/Hardware Codesign 基于软硬件协同设计的栅格后量子密码学中数论变换的高级综合实现与基准测试

International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_19

D. Nguyen, V. Dang, K. Gaj

引用次数: 21

SysIDLib: A High-Level Synthesis FPGA Library for Online System Identification SysIDLib:用于在线系统识别的高级综合FPGA库

International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_8

Gökhan Akgün, Habib ul Hasan Khan, M. Hebaish, M. Elshimy, M. A. E. Ghany, D. Göhringer

引用次数: 2

Optimising Operator Sets for Analytical Database Processing on FPGAs fpga上分析数据库处理的算子集优化

International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_3

Anna Drewes, J. Joseph, B. Gurumurthy, David Broneske, G. Saake, Thilo Pionteck

引用次数: 3

RISC-V Based MPSoC Design Exploration for FPGAs: Area, Power and Performance 基于RISC-V的fpga MPSoC设计探索:面积、功耗和性能

International Workshop on Applied Reconfigurable Computing Pub Date : 2020-04-01 DOI: 10.1007/978-3-030-44534-8_15

Muhammad Ali, P. Rad, D. Göhringer

引用次数: 5