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2019 41st Annual EOS/ESD Symposium (EOS/ESD)最新文献

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Design of a Critical Application Air Ionizer for Semiconductor Manufacturing 半导体制造关键应用空气电离器的设计
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8869967
L. Levit, Gregory Larson, Timothy Maroni, A. Mccall, J. Montoya, Geoffrey Weil, Jeremy Willden
{"title":"Design of a Critical Application Air Ionizer for Semiconductor Manufacturing","authors":"L. Levit, Gregory Larson, Timothy Maroni, A. Mccall, J. Montoya, Geoffrey Weil, Jeremy Willden","doi":"10.23919/EOS/ESD.2019.8869967","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8869967","url":null,"abstract":"A new alpha/pulsed/air-assisted bar ionizer is described. It utilizes a unique asymmetrical sinusoidal voltage waveform with air flow to deliver ions up to 1 m. It produces discharge times [1] <10 seconds with maximum offset voltage of <±5 V, typical. The bar uses <0.9 lpm of air /cm. of bar. Since it has no chemical interactions, it is suitable for certification up to Class 1.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"58 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126149007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EOS/ESD 2019 TOC
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/eos/esd.2019.8870007
{"title":"EOS/ESD 2019 TOC","authors":"","doi":"10.23919/eos/esd.2019.8870007","DOIUrl":"https://doi.org/10.23919/eos/esd.2019.8870007","url":null,"abstract":"","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130873766","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
External Latchup Risks and Prevention Solutions in Advanced Bulk FinFET Technology 先进体FinFET技术中的外部锁存风险及预防方案
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8869999
Wei Liang, R. Gauthier, S. Mitra, Hien Lai
{"title":"External Latchup Risks and Prevention Solutions in Advanced Bulk FinFET Technology","authors":"Wei Liang, R. Gauthier, S. Mitra, Hien Lai","doi":"10.23919/EOS/ESD.2019.8869999","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8869999","url":null,"abstract":"Internal Latchup (ILU) and External Latchup (ELU) are studied in advanced bulk FinFET technology. ELU risks of thin oxide (SG) and thick oxide (EG) devices are assessed and discussed. In this work we present different design techniques which designers can use to eliminate ELU risks in their designs.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129269114","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Low-Leakage NMOS Clamps with Gate-Assisted Bipolar Triggering 低泄漏NMOS钳与门辅助双极触发
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8869969
M. Stockinger
{"title":"Low-Leakage NMOS Clamps with Gate-Assisted Bipolar Triggering","authors":"M. Stockinger","doi":"10.23919/EOS/ESD.2019.8869969","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8869969","url":null,"abstract":"NMOS clamps with gate-assisted bipolar triggering are introduced offering low-leakage, area-efficient ESD protection solutions in a 40nm CMOS technology. Test chip results demonstrate >6kV PESD performance with direct pin discharge, as well as excellent HBM and CDM robustness.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126138910","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Transient Overshoot of Sub-10nm Bulk FinFET ESD Diodes with S/D Epitaxy Stressor 带有S/D外延应力源的亚10nm块体FinFET ESD二极管的瞬态超调
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8870001
Shih-Hung Chen, D. Linten, G. Hellings, Marko Simicic, T. Chiarella, P. Eyben, S. Kubicek, E. Rosseel, A. Hikavyy, N. Horiguchi
{"title":"Transient Overshoot of Sub-10nm Bulk FinFET ESD Diodes with S/D Epitaxy Stressor","authors":"Shih-Hung Chen, D. Linten, G. Hellings, Marko Simicic, T. Chiarella, P. Eyben, S. Kubicek, E. Rosseel, A. Hikavyy, N. Horiguchi","doi":"10.23919/EOS/ESD.2019.8870001","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8870001","url":null,"abstract":"New process options in CMOS technology scaling often result in degradation of ESD device performance. TCAD simulations bring an in-depth look at the impact of S/D epitaxy process options with channel strain engineering on CDM-time domain turn-on transient overshoot of ESD diodes in next generation bulk FinFET and GAA technologies.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128412047","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Comprehensive Physical Model for PNP based ESD Protection Devices in SOI technology SOI技术中基于PNP的ESD保护器件的综合物理模型
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8869987
Xiaolian Han, S. Zhao
{"title":"A Comprehensive Physical Model for PNP based ESD Protection Devices in SOI technology","authors":"Xiaolian Han, S. Zhao","doi":"10.23919/EOS/ESD.2019.8869987","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8869987","url":null,"abstract":"This paper presents a comprehensive physical model for PNP based ESD protection device. The model includes all major physical effects of device during ESD operation, which enables the model to capture the DC, AC and dynamic effects like overshoot, reverse recovery and self-heating. The simulation results have been verified using DC, TLP, vf-TLP and HBM measurements. This model gives good agreement between simulation and measurement in DC, AC and transient conditions. Due to its highly physical nature, the scalability of the model is also ensured.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127397010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Energy of CDM Failure for ICs on Package-, Wafer-and Board-Level 封装级、晶圆级和板级集成电路的CDM失效能量
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8869989
Lena Zeitlhoefler, F. Nieden, K. Esmark, G. Langguth, F. Kreupl
{"title":"Energy of CDM Failure for ICs on Package-, Wafer-and Board-Level","authors":"Lena Zeitlhoefler, F. Nieden, K. Esmark, G. Langguth, F. Kreupl","doi":"10.23919/EOS/ESD.2019.8869989","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8869989","url":null,"abstract":"An energy-based failure is analyzed for Charged-Device-Model-like (CDM) discharges. The stress of an electrostatic discharge (ESD) element can be quantified and simulated, if the background capacitance of an IC domain is known. Differences between package-, wafer- and board-level are evaluated using the Capacitively Coupled Transmission Line Pulsing (CCTLP) method. The difference in the switching behavior of an ESD element due to capacitance relations is evaluated on package- and wafer-level.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126254896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
3.3V ESD Clamp structure susceptibility towards Pseudo Latch Up in 22nm FDSOI 22nm FDSOI中3.3V ESD钳位结构对伪锁存的敏感性
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8869995
Anurag Mittal, N. Bansal, A. Loiseau, Ahmed Y. Ginawi, Wei Liang, Shameer Basha Yerragudi
{"title":"3.3V ESD Clamp structure susceptibility towards Pseudo Latch Up in 22nm FDSOI","authors":"Anurag Mittal, N. Bansal, A. Loiseau, Ahmed Y. Ginawi, Wei Liang, Shameer Basha Yerragudi","doi":"10.23919/EOS/ESD.2019.8869995","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8869995","url":null,"abstract":"An unexpected failure occurred during Latch-Up test of a 22FDSOI chip which had 3.3V general purpose I/Os implemented using 1.8V compliant devices. The high supply current flowing was not a real LU failure but due to triggering of RC clamp during negative current injection on nearby I/Os. The pseudo Latch-Up is presented along with methods to ensure robustness of 3.3V clamp design structures","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"185 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131406426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EOS/ESD 2019 General Chair Letter EOS/ESD 2019总主席信
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/eos/esd.2019.8869974
{"title":"EOS/ESD 2019 General Chair Letter","authors":"","doi":"10.23919/eos/esd.2019.8869974","DOIUrl":"https://doi.org/10.23919/eos/esd.2019.8869974","url":null,"abstract":"","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114493678","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Towards a TCAD Model for NMOS Drivers in 28FDSOI under TLP & (vf)-TLP Transient Condition TLP & (vf)-TLP瞬态条件下28FDSOI NMOS驱动器的TCAD模型
2019 41st Annual EOS/ESD Symposium (EOS/ESD) Pub Date : 2019-09-01 DOI: 10.23919/EOS/ESD.2019.8870008
Siddharth Dhar, J. Bourgeat, C. Parthasarathy
{"title":"Towards a TCAD Model for NMOS Drivers in 28FDSOI under TLP & (vf)-TLP Transient Condition","authors":"Siddharth Dhar, J. Bourgeat, C. Parthasarathy","doi":"10.23919/EOS/ESD.2019.8870008","DOIUrl":"https://doi.org/10.23919/EOS/ESD.2019.8870008","url":null,"abstract":"This work analyzes the TLP and (vf)-TLP characteristics of NMOS driver design in FDSOI technology. A TCAD model based on electro-thermal simulations is developed, that captures the measured characteristics in single NMOS drivers in ON/OFF state conditions, and validated against two different driver configurations. A universal failure criterion based on temperature is demonstrated.","PeriodicalId":233379,"journal":{"name":"2019 41st Annual EOS/ESD Symposium (EOS/ESD)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132059226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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