First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)最新文献_第7页

A Self-Tuning Analog Proportional-Integral-Derivative (PID) Controller 一种自整定模拟比例-积分-导数(PID)控制器

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.12

V. Aggarwal, Meng Mao, Una-May O’Reilly

引用次数: 58

A Modular Framework for the Evolution of Circuits on Configurable Transistor Array Architectures. 一种可配置晶体管阵列结构电路演进的模块化框架。

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.8

M. Trefzer, Jörg Langeheine, K. Meier, J. Schemmel

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引用次数: 5

On-Board Partial Run-Time Reconfiguration for Pico-Satellite Constellations 微型卫星星座的星上部分运行时重构

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.54

T. Vladimirova, Xiaofeng Wu

引用次数: 18

Hardware/Software Coevolution of Genome Programs and Cellular Processors 基因组程序和细胞处理器的硬件/软件协同进化

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.51

G. Tempesti, Pierre-André Mudry, G. Zufferey

引用次数: 9

GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small Satellites GEZGIN,GEZGIN-2:地球观测小卫星自适应实时图像处理子系统

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.49

A. Ismailoglu, O. Benderli, S. Yesil, R. Sever, B. Okcan, O. Sengul, R. Öktem

{"title":"GEZGIN & GEZGIN-2: Adaptive Real-Time Image Processing Subsystems for Earth Observing Small Satellites","authors":"A. Ismailoglu, O. Benderli, S. Yesil, R. Sever, B. Okcan, O. Sengul, R. Öktem","doi":"10.1109/AHS.2006.49","DOIUrl":"https://doi.org/10.1109/AHS.2006.49","url":null,"abstract":"GEZGIN and GEZGIN-2 are real-time multi-spectral image processing subsystems developed for BILSAT-1 and RASAT satellites respectively, the first two Earth observing small satellites of Turkey. Main functionality of these subsystems is to compress in real-time multi-spectral images received concurrently from imagers, using JPEG2000 image compression algorithm. The compression features are controlled through user-supplied parameters uploaded in-orbit, so that the compression rate could be adapted to bandwidth, image quality and other mission requirements. GEZGIN employs both reconfigurable hardware and a DSP processor for image processing, where as the more advanced GEZGIN-2 contains full integration of the JPEG2000 processing path plus other image pre-processing features on reconfigurable hardware, hence offering increased performance and full reconfigurability in orbit. Both systems demonstrate space-tailored architectures for implementing image processing functions where adaptability becomes the crucial issue determining robustness, flexibility and survivability of the system","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"77 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131472401","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

Power Driven Reconfigurable Complex Continuous Wavelet Transform 功率驱动可重构复连续小波变换

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.58

N. Aydin, T. Arslan

引用次数: 0

Hardware Accelerators for Evolving Building Block Modules for Artificial Brains 用于人工大脑构建模块进化的硬件加速器

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.50

H. D. Garis

{"title":"Hardware Accelerators for Evolving Building Block Modules for Artificial Brains","authors":"H. D. Garis","doi":"10.1109/AHS.2006.50","DOIUrl":"https://doi.org/10.1109/AHS.2006.50","url":null,"abstract":"Summary form only given. This paper argues that it is technologically possible to build artificial brains at relatively low cost. The proposed approach to doing this is to evolve large numbers (tens of thousands) of neural network modules, each with its own simple function, and then interconnect them inside a computer that would execute the neural signaling of the whole brain in real time, performing functions such as controlling the behaviors of a robot. The modules could be configured automatically using evolutionary algorithms, by a successive reconfiguration on field programmable gate arrays (FPGA), placed on commercially available boards such as those offered by Celoxica. These chips could be programmed using high level languages, such as \"Handel-C\", whose statements are \"hardware compiled\" into the chip configuring instructions to wire up the chip, speeding-up the execution of instructions. The major challenge of this approach is architecting the artificial brain - how to put 10,000s of evolved neural net modules together to perform a library of controllable behaviors. One potential concern of this approach relates to the anticipated unwanted synergy of inter module neural signaling. While most current artificial brain projects use supercomputers or PC clusters with 1000s of nodes, Moore's law facilitates increasingly larger computational power at low costs, making brain building technically and economically possible. Examples from our efforts in evolving neural modules are presented, along with a critical analysis of the state of the art and realistic assessment of the challenges ahead","PeriodicalId":232693,"journal":{"name":"First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132363327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Systolic Array Based Adaptive Beamformer Modeling in SystemC Environment SystemC环境下基于收缩阵列的自适应波束形成器建模

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.70

O. Tamer, Ahmet Özkurt

引用次数: 0

Wormhole Routing with Virtual Channels using Adaptive Rate Control for Network-on-Chip (NoC) 基于自适应速率控制的片上网络虚拟通道虫洞路由

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-15 DOI: 10.1109/AHS.2006.79

I. Nousias, T. Arslan

引用次数: 27

An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter 一种高效的H.264自适应去块滤波器硬件结构

First NASA/ESA Conference on Adaptive Hardware and Systems (AHS'06) Pub Date : 2006-06-01 DOI: 10.1109/AHS.2006.20

M. Parlak, Ilker Hamzaoglu

引用次数: 13