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48th Midwest Symposium on Circuits and Systems, 2005.最新文献

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Using finite impulse response feedback DACs to design /spl Sigma//spl Delta/ modulators based on LC filters 利用有限脉冲响应反馈dac设计基于LC滤波器的/spl Sigma//spl Delta/调制器
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 2005-08-01 DOI: 10.1109/MWSCAS.2005.1594196
N. Beilleau, H. Aboushady, M. Louerat
{"title":"Using finite impulse response feedback DACs to design /spl Sigma//spl Delta/ modulators based on LC filters","authors":"N. Beilleau, H. Aboushady, M. Louerat","doi":"10.1109/MWSCAS.2005.1594196","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594196","url":null,"abstract":"This paper proposes a general method to design the noise-transfer-function of a continuous-time /spl Sigma//spl Delta/ modulator having high-order passive LC loop filters. The feedback signals can have arbitrary shapes and can be applied either at internal nodes or only at the input node. As a design example, this technique is used to design a 4th order /spl Sigma//spl Delta/ modulator where the internal nodes of the loop filter are removed for a more efficient circuit implementation.","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122170309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
CMOS surface acoustic wave oscillators CMOS表面声波振荡器
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 2005-08-01 DOI: 10.1109/MWSCAS.2005.1594174
A. Nordin, M. Zaghloul, C. Korman, S. Ahmadi
{"title":"CMOS surface acoustic wave oscillators","authors":"A. Nordin, M. Zaghloul, C. Korman, S. Ahmadi","doi":"10.1109/MWSCAS.2005.1594174","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594174","url":null,"abstract":"In this paper we describe the design and implementation of a CMOS surface acoustic wave (SAW) oscillator. The oscillator utilizes surface acoustic wave resonators implemented in both 1.6micron and 0.5micron AMI CMOS process and fabricated through MOSIS. When connected to Pierce oscillator circuits, these resonators are capable of synthesizing frequencies in the range of 400MHz to 1GHz. This paper also addresses the design issues involving codesigning micromachined resonators with CMOS circuitry to optimize the oscillator design","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"252 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123390007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evaluation of a network on chip architecture based on the clockwork routed Manhattan street network using hardware emulation 基于时钟路由曼哈顿街道网络的片上网络架构的硬件仿真评估
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 2005-08-01 DOI: 10.1109/MWSCAS.2005.1594428
K. Oommen, D. Harle
{"title":"Evaluation of a network on chip architecture based on the clockwork routed Manhattan street network using hardware emulation","authors":"K. Oommen, D. Harle","doi":"10.1109/MWSCAS.2005.1594428","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594428","url":null,"abstract":"Trends in integrated circuit design indicate a shift in focus from computation to communication. Interconnect issues within devices now come to the fore as the dedicated wire and shared-bus architectures look increasingly ill-equipped to cope with such complexity. This paper proposes a scalable network on chip architecture based on the Manhattan street network (MSN) using clockwork (CW) routing scheme. The proposed solution is self routing and allows for the implementation of routing functionality in hardware, eliminating the need for custom routing tables at each node. In this study, the characteristics of the proposed architecture are evaluated based upon the first full hardware implementation of a functional MSN-CW. Due to the deterministic nature of the routing mechanism, upper bounds on network delay can be established. This makes the architectures particularly suited to applications involving realtime constraints","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"158 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116514263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Automatic biasing point extraction and design plan generation for analog IPs 模拟ip的自动偏置点提取和设计方案生成
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 2005-08-01 DOI: 10.1109/MWSCAS.2005.1594249
R. Iskander, A. Kaiser, M. Louerat
{"title":"Automatic biasing point extraction and design plan generation for analog IPs","authors":"R. Iskander, A. Kaiser, M. Louerat","doi":"10.1109/MWSCAS.2005.1594249","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594249","url":null,"abstract":"In this paper, an algorithm for automatic extraction of DC biasing point towards generation of design plans is presented. Initially, the circuit is described as a hierarchy of modules and devices inside our dedicated framework CAIRO+. Electrical information is propagated from higher level modules, to lower level ones, till reaching the device level. During navigation through the hierarchy, a dependency subgraph is generated for each device and module. Each subgraph expresses electrical dependencies by choosing among a set of predefined sizing operators. To obtain a final directed acyclic graph, existing graph directed cycles are detected and removed. The resulting graph represents the complete sizing procedure for the analog IP. The calculated biasing point is compared against operating point simulation. The algorithm is successfully applied to two analog IPs: single-ended two-stages output transconductance amplifier and differential cascode current-mode integrator","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130585105","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
On performance improvement of stereophonic acoustic echo cancellation through the use of hybrid structure 利用混合结构提高立体声回声消除性能的研究
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 2005-07-01 DOI: 10.1109/MWSCAS.2005.1594487
B. Krittayanun, N. Tangsangiumvisai
{"title":"On performance improvement of stereophonic acoustic echo cancellation through the use of hybrid structure","authors":"B. Krittayanun, N. Tangsangiumvisai","doi":"10.1109/MWSCAS.2005.1594487","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594487","url":null,"abstract":"This paper proposes an adaptive filtering algorithm for stereophonic acoustic echo cancellation (SAEC) in order to obtain computational complexity reduction and convergence rate improvement. The hybrid mono/stereo structure between fast affine projection (FAP) and frequency-domain normalized least mean square (F-NLMS) algorithms is introduced, based on subband processing. Simulation results on recorded speech signals suggest that convergence rate can be improved at low computational cost.","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131166654","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PWM switch model of a buck-boost converter operated under discontinuous conduction mode 断续导通模式下buck-boost变换器的PWM开关模型
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 1900-01-01 DOI: 10.1109/MWSCAS.2005.1594189
A. Reatti, M. Balzani
{"title":"PWM switch model of a buck-boost converter operated under discontinuous conduction mode","authors":"A. Reatti, M. Balzani","doi":"10.1109/MWSCAS.2005.1594189","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594189","url":null,"abstract":"A small-signal circuit model for PWM dc-dc converters operated in discontinuous conduction mode DCM is presented. The model is composed of controlled current sources, and resistances. The principle of energy conservation approach is utilized to take into account parasitic resistances of the transistor and diode and the diode threshold voltage. The proposed model is suitable for small-signal, frequency-domain representation of the converters. This model is used to derive the expressions for a buck-boost converter control-to-output transfer function, input-to-output voltage transfer function, input impedance, and the output impedance. Bode plots are also given for these transfer functions","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115386224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Synthesis methodology for transimpedance amplifier with bit error rate constraint 具有误码率约束的跨阻放大器的综合方法
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 1900-01-01 DOI: 10.1109/MWSCAS.2005.1594088
M. El-Nozahi, Y. Massoud
{"title":"Synthesis methodology for transimpedance amplifier with bit error rate constraint","authors":"M. El-Nozahi, Y. Massoud","doi":"10.1109/MWSCAS.2005.1594088","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594088","url":null,"abstract":"In this paper, we present a new knowledge based synthesis methodology that facilitates the automatic design of maximum bandwidth transimpedance amplifier (TIA) for optical communications under the constraint of a specific bit error rate. Our synthesis methodology is based on newly developed models that characterize the input referred noise and bandwidth. Our technique predicts the required optimum transimpedance parameter values to maximize the bandwidth. These optimum parameters are mapped to some circuit parameters for automatically sizing the TIA. Our methodology is characterized by its fast design convergence compared to conventional design techniques. We apply our synthesis methodology to design a TIA for optical interconnect system and we obtained a five fold increase in the transimpedance gain as compared to the previous work","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121104060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of phase noise of saturated ring oscillators 饱和环形振荡器相位噪声分析
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 1900-01-01 DOI: 10.1109/MWSCAS.2005.1594416
F. Yuan
{"title":"Analysis of phase noise of saturated ring oscillators","authors":"F. Yuan","doi":"10.1109/MWSCAS.2005.1594416","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594416","url":null,"abstract":"An in-depth review of the methods for phase noise analysis of saturated ring oscillators is presented. The assumption and limitation of the methods are investigated in detail. The framework of an efficient analysis method for the phase noise of saturated ring VCOs is presented. The method is based on the theory of periodically time-varying systems, in particular, the response of periodically time-varying systems to stochastic inputs. We show that both the up-conversion of low-frequency noise and down-conversion of broadband noise can be treated conveniently. The method provides an insight on how device noise is converted to the overall phase noise (timing jitter) of saturated oscillators","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127374960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High accuracy differential capacitive circuit for bioparticles sensing applications 高精度差分电容电路，用于生物颗粒传感应用
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 1900-01-01 DOI: 10.1109/MWSCAS.2005.1594363
E.G. Zadeh, M. Sawan
{"title":"High accuracy differential capacitive circuit for bioparticles sensing applications","authors":"E.G. Zadeh, M. Sawan","doi":"10.1109/MWSCAS.2005.1594363","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594363","url":null,"abstract":"A linear differential capacitive circuit is presented. This circuit is based on a charge-based capacitance measurement (CBCM) technique. The proposed circuit is optimized so as to maximize the sensitivity, which is a critical parameter in capacitive sensors. The resulting sensitivity is 200mV/fF with a noise level equivalent to 5aF. This circuit is intended as an interface circuit for bioparticles detection in integrating with a microchannel which is fabricated in a new robotic based technique","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127546234","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Fuzzy logic based particle filter for tracking a maneuverable target 基于模糊逻辑的粒子滤波跟踪机动目标
48th Midwest Symposium on Circuits and Systems, 2005. Pub Date : 1900-01-01 DOI: 10.1109/MWSCAS.2005.1594407
H. Kamel, Wael Badawy
{"title":"Fuzzy logic based particle filter for tracking a maneuverable target","authors":"H. Kamel, Wael Badawy","doi":"10.1109/MWSCAS.2005.1594407","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594407","url":null,"abstract":"In this paper we propose a new fuzzy logic-based particle filter (FLPF) algorithm for tracking a maneuvering target. The nonlinear system which is comprised of two-input and single-output are presented by fuzzy relational equations. Each of the fuzzy relational equations is expressed in a canonical-rule based form. The dynamics of the maneuvering target are modeled by multiple switching (jump Markov) systems. We assume that the target follows one-out-of-three dynamic behavior model at any time in the observation period: constant velocity (CV) motion model, clockwise coordinated turn (CCT) model, and anticlockwise coordinated turn (ACT) model. The time-varying deviation between actual and predicted positions is inferred by a two-input single-output fuzzy relation. An example is included for visualizing the effectiveness of the proposed algorithm. For comparison purposes, we simulated a conventional sequential importance sampling (SIS) algorithm. Simulation results showed that the FLPF has better tracking performance compared to the SIS.","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"19 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125852954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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