48th Midwest Symposium on Circuits and Systems, 2005.最新文献

{"title":"FPGA implementation of a stereo matching processor based on window-parallel-and-pixel-parallel architecture","authors":"M. Hariyama, Y. Kobayashi, Haruka Sasaki, M. Kameyama","doi":"10.1093/ietfec/e88-a.12.3516","DOIUrl":"https://doi.org/10.1093/ietfec/e88-a.12.3516","url":null,"abstract":"This paper presents a processor architecture for high-speed and reliable stereo matching based on adaptive window-size control of SAD (sum of absolute differences) computation. To reduce its computational complexity, SADs are computed using images divided into nonoverlapping regions, and the matching result is iteratively refined by reducing a window size. Window-parallel-and-pixel-parallel architecture is also proposed to achieve to fully exploit the potential parallelism of the algorithm. The architecture also reduces the complexity of an interconnection network between memory and functional units based on the regularity of reference pixels. The stereo matching processor is implemented on an FPGA. Its performance is 80 times higher than that of a microprocessor (Pentium4@2GHz), and is enough to generate a 3D depth image at the video rate of 33MHz","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124902457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A novel ultrafine particle measurement system with an electrometer","authors":"Sang-Soo Park, Chang-Jin Lee, Soo-Won Kim, Seungbok Lee, Gwi-Narn Bae, K. Moon","doi":"10.1109/MWSCAS.2005.1594080","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594080","url":null,"abstract":"In this study, a novel ultra fine particle measurement system using condensation and charging techniques was proposed. It consisted of the inlet/size separation part for selecting particles in the bounded-size range, a uniform growth unit for deriving the condensation of ultra fine particles, an aerosol charger for charging particles grown uniformly in the growth unit, a Faraday cage/ammeter part for measuring ultra low current about 10-13 A induced by charged-particles collected on the filter in Faraday cage, and a communication network part for monitoring particle data in real time. The particle phenomena occurred in major components of the ultra fine particle measurement system was introduced and the ammeter circuit used in this work was described in detail. The performance of the prototype ammeter was comparable with a commercial one","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114870816","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design of readout IC for uncooled infrared bolometer sensor using bias offset correction technique","authors":"Sang Won Park, S. Hwang, E. Jung, M. Sung","doi":"10.1109/MWSCAS.2005.1594135","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594135","url":null,"abstract":"Infrared bolometer sensor's variation is detected by voltage drop between reference resistor and bolometer resistor in this architecture. One of the serious problems in this architecture is that these resistors value has a process variation. So common-mode level could be different from expectation in room temperature. Different common-mode level could lead to wrong output at the end of readout circuit. We suggest useful method to solve this problem. Difference correction using capacitor has reduced CM level difference to 86 % for 1 MOmega bolometer and reference resistor's 10 % variation","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131612081","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A stable n-channel mirrorable current source for versatile analog design with thin film transistors","authors":"S. Sambandan, A. Nathan","doi":"10.1109/MWSCAS.2005.1594231","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594231","url":null,"abstract":"Amorphous silicon (a-Si:H) thin film transistors (TFTs) are widely used as the active element in large area sensor and display systems. Circuit design with the TFT is constrained by the absence of p-channel devices, and thereby a current source, due to low device mobility. Moreover, the device is also prone to a bias dependent threshold voltage instability. We present a mirrorable current source built with only n-channel devices, which is immune to the variation in threshold voltage, thereby effectively increasing the application spectrum of the TFT","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"11 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131853570","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Reconfigurable state-machine oriented flow-based router design","authors":"D. Guha, Seng-Kyoun Jo, Doan Huy Cuong, Yang Ok Sik, J. Choi, Minakshi Kumar, Saurabh Lal","doi":"10.1109/MWSCAS.2005.1594330","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594330","url":null,"abstract":"Traditional Internet protocol (IP) address lookup is one of the major performance bottlenecks in high-end routers. Prior art has investigated into architectures for flow-based IP address lookup engines based on programmable finite state machines (FSMs), which when implemented in a regular structured hardware engine, has led to the classical update problem in improving the reprogramming time of each machine and effective scheduling of the individual machines in the context of router database update. This paper describes a distributed co-evolving architecture that looks into the issue of an optimal hardware-software partition for flow-based routing from the viewpoint of memory and resource optimizations","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116587272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Efficient external memory segment intersection for processing very large VLSI layouts","authors":"R. Sharathkumar, M. Vinaykumar, P. Maheshwari, P. Gupta","doi":"10.1109/MWSCAS.2005.1594207","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594207","url":null,"abstract":"One fundamental problem that arises in VLSI layout analysis and verification is the segment intersection problem: given a set of segments in the plane, find all pairwise intersections. This problem has been widely studied in the Computational Geometry. One problem with processing large VLSI layouts is that the data to be processed may be far too massive to fit in main memory. When dealing with data sets of sizes exceeding main memory, communication between the fast internal memory and the slow external memory is often the performance bottleneck and algorithms and data structures designed under the assumption of a single level of memory may be meaningless. External-memory algorithms try to optimize performance by taking into account disk accesses. One can certainly use the standard main memory algorithms for data that reside on disk but their performance is often considerably below the optimum because there is no control over how the operating system performs disk accesses. On demand thrashing can be high thus resulting in an increase in response time. Although a lot of research has been done in the recent past on efficient external-memory algorithms and data structures, such work in the area of VLSI computer-aided design is limited. We have designed and implemented a practical external-memory algorithm for reporting all intersecting pairs amongst a set of orthogonal segments. The key to our success is that we take advantage of the fact that real data sets from VLSI applications tend to obey the so-called \"square-root\" rule, i.e. in a set of TV line segments, the expected number of line segments intersecting a horizontal or vertical scanline in a VLSI layout is O(radic N), a fact ignored by known external-memory algorithms. Another factor that is crucial to our success is that other algorithms stores the data structures in external memory requiring I/O to access them. We reduce such disk accesses by using a clever storage scheme. Our algorithm outperforms not only a standard in-memory algorithm but also an existing external-memory algorithm for segment intersection reporting","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Address code generation utilizing memory sharing in DSP processors","authors":"Taewhan Kim, Shin Hong","doi":"10.1109/MWSCAS.2005.1594167","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594167","url":null,"abstract":"We propose an effective address code generation algorithm for digital signal processing (DSP) processors to minimize the size of addressing code. Unlike the traditional design flow in which the memory sharing for variables in code and the address (offset) assignment for the variables are performed sequentially without any interaction between them (mainly due to the high problem complexity to solve), our work attempts to tightly couple the memory sharing with offset assignment to exploit memory sharing on optimizing addressing instructions more effectively. We accomplish this by proposing a new integrated algorithm for memory sharing and address code generation that leads to efficient sequence of variable accesses, minimizing addressing instructions. Experimental results show average reduction of 10.8% in the address code size over that by the conventional approach","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134521445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design and simulation of aluminum bifunctional spatial light modulator","authors":"X. Xiong, T. Dallas, S. Gangopadhyay, J. Berg, T. Henryk","doi":"10.1109/MWSCAS.2005.1594063","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594063","url":null,"abstract":"In this paper, a bifunctional aluminum MEMS spatial light modulator (micromirror) device design is introduced. The bifunctional mirror can work in both torsional and piston modes, depending on the voltage applied to the bottom driving electrodes. The mirror was fabricated with thick photoresist sacrificial layer technique. The working principle and performance of the micromirror are analyzed. Based upon the analysis, an optimized micromirror design is proposed. The mirror can deflect for a maximum displacement of 1.3/spl mu/m in its piston mode, and rotate for a maximum angle of 3.1/spl deg/ in its torsional mode. The micromirror can be used to modulate the phase as well as the direction of the incident light due to its bifunctional modes.","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127758281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Dynamic reconfigurable distributed processing network with dual levels of operand granularity","authors":"F. M. Vallina, E. Oruklu, J. Saniie","doi":"10.1109/MWSCAS.2005.1594325","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594325","url":null,"abstract":"This paper introduces a platform capable of handling varying operand sizes across a set of algorithms to be accelerated by a low power hardware core. The key to dealing with different levels of operand granularity is to implement them on the reconfigurable distributed processing network (RDPN), which can handle dynamic changes to operand size. This approach allows algorithms which may be incompatible for the same hardware platform to be accelerated by a common hardware core. This acceleration core based on the RDPN allows algorithms of different levels in operand granularity to be accelerated by a low power system without the need for extra logic. The RDPN architecture provides a flexible platform, which bridges the gap between software and hardware by extending the applicability of an embedded hardware system. This extended applicability is a result of the native support for word size extension and contraction within the RDPN computational fabric. A case study from the signal processing algorithmic domain will be presented to show how the RDPN fabric dynamically adapts to the operand granularity required by different stages of an algorithm","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133732834","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A high linearity, efficient bandwidth, and high stability transimpedance amplifier","authors":"D. B. Yen Nguyen, Quan Le, Y. Oh, H. Le, Sang-Gug Lee","doi":"10.1109/MWSCAS.2005.1594065","DOIUrl":"https://doi.org/10.1109/MWSCAS.2005.1594065","url":null,"abstract":"This paper presents a new high performance wideband CMOS transimpedance amplifier (TIA) for 2.5 Gbps optical transceiver. Our proposed TIA self-regulating adjusts the controllable inductive peeking load and feedback resistances whenever overload condition occurs. The proposed TIA design exhibits bandwidth enhancement, lower input referred noise, and higher amplifier stability. This TIA has 69 dBOmega gain at 3 dB bandwidth, 7.2 pA/radicHz input referred noise and good performance of eye diagram. The TIA operates at the 3.3 V supply voltage, and dissipates about 34 mA for whole circuit. The simulation is accomplished with 1 pF capacitance and 0.85 A/W responsibility photodiode model","PeriodicalId":231135,"journal":{"name":"48th Midwest Symposium on Circuits and Systems, 2005.","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127347629","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}