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25th ACM/IEEE, Design Automation Conference.Proceedings 1988.最新文献

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Automatic insertion of BIST hardware using VHDL 使用VHDL自动插入BIST硬件
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14727
Kwanghyun Kim, J. Tront, D. Ha
{"title":"Automatic insertion of BIST hardware using VHDL","authors":"Kwanghyun Kim, J. Tront, D. Ha","doi":"10.1109/DAC.1988.14727","DOIUrl":"https://doi.org/10.1109/DAC.1988.14727","url":null,"abstract":"A system is presented which automatically inserts BIST (built-in self-testing) hardware to a circuit described in VHDL (VHSIC Hardware Description Language). An appropriate VHDL modeling style for automatic insertion of BIST hardware is investigated. The use of BILBO (built-in logic block observer) is primarily pursued in the system. Algorithmic and rule-based approaches are used in the insertion of BILBO. Test scheduling and control signal distribution are also performed by the system.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116306945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
A digital-serial silicon compiler 数字串行硅编译器
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14834
Richard Hartley, Peter F. Corbett
{"title":"A digital-serial silicon compiler","authors":"Richard Hartley, Peter F. Corbett","doi":"10.1109/DAC.1988.14834","DOIUrl":"https://doi.org/10.1109/DAC.1988.14834","url":null,"abstract":"A novel silicon compiler is described, called PARSIFAL. It constructs chips with a data-flow architecture in which data is passed in a digit-wide pipeline form one computational element to the next. The size of a digit can be specified by the user to be any value between one and the full word size of the chip. A digit size of one gives bit-serial chips, whereas a digit-size equal to the word-size gives fully parallel computation. It is shown that an intermediate value of the digit-size usually gives the most efficient chips in terms of throughput per unit area.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131611444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 46
Fast algorithm for optimal layer assignment 最优层分配的快速算法
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14815
Y. Kuo, T. C. Chern, W. Shih
{"title":"Fast algorithm for optimal layer assignment","authors":"Y. Kuo, T. C. Chern, W. Shih","doi":"10.1109/DAC.1988.14815","DOIUrl":"https://doi.org/10.1109/DAC.1988.14815","url":null,"abstract":"Given the geometry of wires for interconnections, the authors want to assign two conducting layers to the segments of these wires so that the number of vias required is minimized. This layer assignment problem, also referred to as the via minimization problem, has been formulated as finding a maximum cut of a planar graph. The authors propose a novel algorithm for optimal layer assignment under a general model where the planar graph has real-valued edge weights. The time complexity of the proposed algorithm is O(n/sup 3/2/ log n) where n is the number of wire-segment clusters in a given layout. In contrast, all existing optimal algorithms for layer assignment have the time complexity of O(n/sup 3/).<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132181126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
A path selection algorithm for timing analysis 时序分析的路径选择算法
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14850
H. C. Yen, S. Ghanta, D. Du
{"title":"A path selection algorithm for timing analysis","authors":"H. C. Yen, S. Ghanta, D. Du","doi":"10.1109/DAC.1988.14850","DOIUrl":"https://doi.org/10.1109/DAC.1988.14850","url":null,"abstract":"Existing algorithms for timing analysis have difficulties when dealing with large designs. A novel algorithm for timing analysis is proposed that enumerates all the paths with delay greater than a given threshold. The execution time of the proposed algorithm is proportional to the number of paths generated, so it is suitable for large designs.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115385729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 26
Spare allocation and reconfiguration in large area VLSI 大面积超大规模集成电路中的备用分配与重构
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14826
S. Kuo, Kent Fuchs
{"title":"Spare allocation and reconfiguration in large area VLSI","authors":"S. Kuo, Kent Fuchs","doi":"10.1109/DAC.1988.14826","DOIUrl":"https://doi.org/10.1109/DAC.1988.14826","url":null,"abstract":"A summary of systematic approach developed by the authors for spare allocation and reconfiguration is presented. Spare allocation is modeled in graph-theoretic terms in which spare allocation for a specific reconfigurable system is shown to be equivalent to either a graph-matching or a graph-dominating-set problem. The complexity of optimal spare allocation for each of the problem classes is analyzed, and reconfiguration algorithms are provided.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117182604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Logic simulation system using simulation processor (SP) 基于仿真处理器(SP)的逻辑仿真系统
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14762
Minoru Saitoh, K. Iwata, Akiko Nokamura, M. Kakegawa, J. Masuda, H. Hamamura, F. Hirose, N. Kawato
{"title":"Logic simulation system using simulation processor (SP)","authors":"Minoru Saitoh, K. Iwata, Akiko Nokamura, M. Kakegawa, J. Masuda, H. Hamamura, F. Hirose, N. Kawato","doi":"10.1109/DAC.1988.14762","DOIUrl":"https://doi.org/10.1109/DAC.1988.14762","url":null,"abstract":"A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122581164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performance “天鹅绒”性能的向量化逻辑仿真与评估算法
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14763
Y. Kazama, Yoshiaki Kinoshita, Motonobu Nagafuji, H. Murayama
{"title":"Algorithm for vectorizing logic simulation and evaluation of 'VELVET' performance","authors":"Y. Kazama, Yoshiaki Kinoshita, Motonobu Nagafuji, H. Murayama","doi":"10.1109/DAC.1988.14763","DOIUrl":"https://doi.org/10.1109/DAC.1988.14763","url":null,"abstract":"A very-large-scale logic simulation engine called VELVET has been developed. VELVET is a vectorized event-driven simulator which can handle simultaneously both gate-level logic and register-transfer level structure. VELVET can process simulation jobs two orders of magnitude faster than a conventional gate-level simulator. A description is given of how to realize such high performance. An algorithm is presented for vectorizing the simulation and performance.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126875205","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Verification of VHDL designs using VAL 用VAL验证VHDL设计
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14733
L. M. Augustin, B. Gennart, Youm Huh, D. Luckham, A. Stanculescu
{"title":"Verification of VHDL designs using VAL","authors":"L. M. Augustin, B. Gennart, Youm Huh, D. Luckham, A. Stanculescu","doi":"10.1109/DAC.1988.14733","DOIUrl":"https://doi.org/10.1109/DAC.1988.14733","url":null,"abstract":"VAL (VHDL Annotation Language) uses a small number of language constructs to annotate VHDL (VHSIC Hardware Description Language) hardware descriptions. VAL annotations, added to the VHDL entity declaration in the form of formal comments, express intended behavior common to all architectural bodies of the entity. The result is a simple but expressive language extension of VHDL with possible applications to automatic checking of VHDL simulations, hierarchical design, and automatic verification of hardware designs in VHDL. An overview is given of design checking using VAL. VAL is described in detail and it is shown how VAL annotations are used to generate constraints on a VHDL simulation. A brief overview of the VAL transformer demonstrates the feasibility of the design. Some observations based on experience with VAL to date and areas for future work are considered.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"9 12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123805276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Clock event suppression algorithm of VELVET and its application to S-820 development 天鹅绒时钟事件抑制算法及其在S-820开发中的应用
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14849
Y. Takamine, Shunsuke Miyamoto, Shigeo Nagashima, Masayuki Miyoshi, S. Kawabe
{"title":"Clock event suppression algorithm of VELVET and its application to S-820 development","authors":"Y. Takamine, Shunsuke Miyamoto, Shigeo Nagashima, Masayuki Miyoshi, S. Kawabe","doi":"10.1109/DAC.1988.14849","DOIUrl":"https://doi.org/10.1109/DAC.1988.14849","url":null,"abstract":"An advanced clock event suppression algorithm for high-speed logic simulation is described. A signal value, Cn, and a current clock (CC), which indicates the current status of clock signals, has been introduced to realize this algorithm. This algorithm suppresses about 60% of the total events, and eliminates 40% of CPU time. No overhead is needed to incorporate this algorithm using hardware support of VELVET (vectorized processing system for logic verification). Hitachi's latest supercomputer S-820 has been developed using VELVET. The development period has been shortened to 3/4 that of the S-810.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131219120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A channelless, multilayer router 一种无信道的多层路由器
25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI: 10.1109/DAC.1988.14839
R. Lunow
{"title":"A channelless, multilayer router","authors":"R. Lunow","doi":"10.1109/DAC.1988.14839","DOIUrl":"https://doi.org/10.1109/DAC.1988.14839","url":null,"abstract":"The authors have implemented a channelless, gridless, multilayer router as part of the Magic IC layout system. The router is designed to handle routing problems associated with emerging technologies such as wafer-scale integration and multilayered metal processes. Three features distinguish this router: rectilinear Steiner trees with floating segments a routing scheduler, and a corner-stitched database.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"152 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116734724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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