基于仿真处理器(SP)的逻辑仿真系统

25th ACM/IEEE, Design Automation Conference.Proceedings 1988. Pub Date : 1988-06-01 DOI:10.1109/DAC.1988.14762

Minoru Saitoh, K. Iwata, Akiko Nokamura, M. Kakegawa, J. Masuda, H. Hamamura, F. Hirose, N. Kawato

{"title":"基于仿真处理器(SP)的逻辑仿真系统","authors":"Minoru Saitoh, K. Iwata, Akiko Nokamura, M. Kakegawa, J. Masuda, H. Hamamura, F. Hirose, N. Kawato","doi":"10.1109/DAC.1988.14762","DOIUrl":null,"url":null,"abstract":"A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<<ETX>>","PeriodicalId":230716,"journal":{"name":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1988-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Logic simulation system using simulation processor (SP)\",\"authors\":\"Minoru Saitoh, K. Iwata, Akiko Nokamura, M. Kakegawa, J. Masuda, H. Hamamura, F. Hirose, N. Kawato\",\"doi\":\"10.1109/DAC.1988.14762\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<<ETX>>\",\"PeriodicalId\":230716,\"journal\":{\"name\":\"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.\",\"volume\":\"42 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1988-06-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DAC.1988.14762\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"25th ACM/IEEE, Design Automation Conference.Proceedings 1988.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DAC.1988.14762","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

描述了一种专用逻辑仿真处理器(SP)和用于验证计算机和其他逻辑器件设计的SP的软件系统。该系统可以评估包含400万个逻辑原语和32mb内存的逻辑电路，最高速度为每秒8亿次有效原语评估。给出了硬件结构的概要，并讨论了优化硬件性能的软件系统。

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Logic simulation system using simulation processor (SP)

A special-purpose logic simulation processor (SP) and a software system for the SP for use in verifying the design of computers and other logic devices are described. The system can evaluate a logic circuit containing 4 million logic primitives and 32 Mbytes of memory at a maximum speed of 800 million active primitive evaluations per second. An outline is given of the hardware architecture, and a software system that optimizes hardware performance is discussed.<>

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来源期刊

25th ACM/IEEE, Design Automation Conference.Proceedings 1988.

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