2021 IEEE International Workshop on Rapid System Prototyping (RSP)最新文献

Implementing Rowhammer Memory Corruption in the gem5 Simulator 在gem5模拟器中实现Rowhammer内存损坏

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/RSP53691.2021.9806242

Loïc France, Florent Bruguier, M. Mushtaq, D. Novo, P. Benoit

引用次数: 2

HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks HyCo:用于光互连网络的低延迟混合控制平面

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/RSP53691.2021.9806198

F. Magalhães, M. Nikdast, Fabiano Hessel, O. Liboiron-Ladouceur, G. Nicolescu

{"title":"HyCo: A Low-Latency Hybrid Control Plane for Optical Interconnection Networks","authors":"F. Magalhães, M. Nikdast, Fabiano Hessel, O. Liboiron-Ladouceur, G. Nicolescu","doi":"10.1109/RSP53691.2021.9806198","DOIUrl":"https://doi.org/10.1109/RSP53691.2021.9806198","url":null,"abstract":"Next-generation multiprocessor systems point to the integration of a large number of cores (e.g., processing and memory) where electrical networks-on-chip (eNoCs) can improve the communication performance. As the number of integrated cores increases, metallic interconnect in eNoCs becomes a bottleneck, leading to communication performance degradation and increased power consumption. Optical interconnection networks (OINs) have emerged to outperform the communication infrastructure in multiprocessor systems. Nevertheless, OINs’ full capability is curbed by high latency electrical controllers required to orchestrate and (re)configure the underlying photonic components, realizing a path between sending and receiving cores. Control techniques impose a high latency to perform the network routing, limiting the full utilization of OINs. In this paper, we design a novel low-latency Hybrid Controller (HyCo) that employs acceleration techniques to reduce its execution time. HyCo is developed based on integrating centralized and distributed control techniques as well as by using pre-calculated network routes and a Bloom filter, all of which result in a considerable reduction in HyCo’s latency. Simulation and prototyping results for networks up to 64×64 indicate a latency smaller than 50 ns, in the worst-case scenario.","PeriodicalId":229411,"journal":{"name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129961704","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

FPGA Prototyping of Systolic Array-based Accelerator for Low-Precision Inference of Deep Neural Networks 基于收缩阵列的深度神经网络低精度推理加速器的FPGA原型设计

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806200

Soobeom Kim, Seunghwan Cho, Eunhyeok Park, S. Yoo

引用次数: 1

Integrating Quick Resource Estimators in Hardware Construction Framework for Design Space Exploration 在设计空间探索硬件构建框架中集成快速资源估算器

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806276

Bruno Ferres, O. Muller, F. Rousseau

引用次数: 1

Prototyping FPGA through overlays 通过覆盖的FPGA原型

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/RSP53691.2021.9806222

Théotime Bollengier, Loïc Lagadec, C. Teodorov

引用次数: 0

Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping Platform 利用传感器在环原型平台开发智能传感器系统的数据增强框架

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806209

Nils Büscher, Daniel Gis, Johann-Peter Wolff, C. Haubelt

{"title":"Data Augmentation Framework for Smart Sensor System Development Using the Sensor-in-the-Loop Prototyping Platform","authors":"Nils Büscher, Daniel Gis, Johann-Peter Wolff, C. Haubelt","doi":"10.1109/rsp53691.2021.9806209","DOIUrl":"https://doi.org/10.1109/rsp53691.2021.9806209","url":null,"abstract":"Sensor subsystems are becoming more complex as they increasingly take on various tasks, from signal processing to pattern recognition. This off-loading of continuous processes can decrease power consumption of the entire system, as the application processor of e.g. a smartwatch can spend more time in low-power modes. The design and validation of these sensor subsystems are thus becoming more difficult and time-consuming. This development process relies heavily on the availability of suitable sensor signals for testing. We propose a modular component-based framework to generate a multitude of tests using either prerecorded sensor signals or artificial signals to allow for a faster and more thorough development process and prototyping.Using the recently proposed Sensor-in-the-Loop architecture, the work at hand demonstrates not only the ability to test and develop the software offline in a simulation, but to also use the augmented sensor signal data directly on the hardware prototype at run-time. The framework can be used in various testing- and development setups to simulate sensor characteristics, processing steps and errors. We show, based on three comprehensive examples, that the proposed framework is able to simulate the common errors found in inertial MEMS sensors, generate signal traces to develop, train, and evaluate gesture recognition algorithms, and simulate pre-processing steps in order to evaluate their feasibility before they are implemented in the sensor firmware.","PeriodicalId":229411,"journal":{"name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124057716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Heterogeneous Logic Implementation for Adders in VTR VTR中加法器的异构逻辑实现

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806205

Harpreet Kaur, Georgiy Krylov, S. A. Damghani, K. Kent

引用次数: 0

An FPGA-based Emulation Platform for Edge Computing Node Design Exploration 基于fpga的边缘计算节点仿真平台研究

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806230

Theo Soriano, D. Novo, P. Benoit

{"title":"An FPGA-based Emulation Platform for Edge Computing Node Design Exploration","authors":"Theo Soriano, D. Novo, P. Benoit","doi":"10.1109/rsp53691.2021.9806230","DOIUrl":"https://doi.org/10.1109/rsp53691.2021.9806230","url":null,"abstract":"Recent advances in machine learning have made it possible to consider the implementation of smart applications in constrained systems at the edge of the network. These memory and Central Processing Unit (CPU) intensive applications may require specific exploration methodologies to design efficient node computing devices. To better guide and validate these explorations, we need to perform energy and performance evaluations of the system. Software-based evaluation tools are application-oriented and do not consider real-time and hardware constraints. Alternatively, hardware prototyping allows an accurate and real-time evaluation but offers limited flexibility and does not allow agile design exploration of the microcontroller unit (MCU). In this work, we propose a Field Programmable Gate Arrays (FPGA) based edge computing node emulation platform. Our solution combines the flexibility and the real-time capability of programmable logic with hardware prototype evaluation. We present an open-source microcontroller architecture for design exploration which integrates an activity monitor to collect traces at run-time. These activity traces are then used to profile the energy consumption of different components in the edge computing node. Importantly, our FPGA is connected to real sensors and communication modules to enable interactions with the environment during the node evaluation and exploration.","PeriodicalId":229411,"journal":{"name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","volume":"189 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115600157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation 模板驱动和以硬件为中心的跨域E/E体系结构仿真

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806231

K. Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker, Max Kramer, C. Reichmann

{"title":"Template-Driven and Hardware-Centric Cross-Domain E/E Architecture Simulation","authors":"K. Neubauer, Leonard Masing, Michael Mahl, Jürgen Becker, Max Kramer, C. Reichmann","doi":"10.1109/rsp53691.2021.9806231","DOIUrl":"https://doi.org/10.1109/rsp53691.2021.9806231","url":null,"abstract":"Due to various trends in the automotive sector, such as autonomous driving and electrification, the number of Electric/Electronic (E/E) components has risen in both hardware and software. This has led to an increase in certification requirements, which cannot be fulfilled without simulation anymore [1]. Different approaches have emerged trying to master this issue. However, for supporting early design decisions in the E/E development, these are either domain-specific or too elaborate. In this paper, we demonstrate an approach to realize early design decisions through a cross-domain simulation of E/E architectures, regarding the environment, scenarios, vehicle physics, the scheduling of software components and the power supply net. We use static E/E architecture hardware models, consisting of Electronic Control Units (ECUs), sensors, actuators and the wiring harness, as the base for the structure of our simulation models. The individual E/E components are linked to parameterizable simulation model templates to facilitate scalable execution. Moreover, scenarios are used for model reduction and supply the simulation model with stimuli. The simulation model is synthesized in an automated manner. For the evaluation, we simulate the power consumption of an electric vehicle, dependent on different loads. It shows that considering hardware aspects in early design phases uncovers errors that would have been noticed much later, e.g. when using virtual Hardware In the Loop (vHIL) methods. We also investigate the scalability of our approach. As E/E architecture modeling tool, we use Vector PREEvision and for the simulation Mathworks Simulink.","PeriodicalId":229411,"journal":{"name":"2021 IEEE International Workshop on Rapid System Prototyping (RSP)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2021-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124488436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Instruction Set Design Methodology for In-Memory Computing through QEMU-based System Emulator 基于qemu系统仿真器的内存计算指令集设计方法

2021 IEEE International Workshop on Rapid System Prototyping (RSP) Pub Date : 2021-10-14 DOI: 10.1109/rsp53691.2021.9806255

Kévin Mambu, H. Charles, J. Dumas, Maha Kooli

引用次数: 2