基于fpga的边缘计算节点仿真平台研究

Theo Soriano, D. Novo, P. Benoit
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引用次数: 1

摘要

机器学习的最新进展使得在网络边缘的受限系统中考虑智能应用程序的实现成为可能。这些内存和中央处理单元(CPU)密集型应用程序可能需要特定的探索方法来设计高效的节点计算设备。为了更好地指导和验证这些探索,我们需要执行系统的能量和性能评估。基于软件的评估工具是面向应用的,不考虑实时和硬件约束。另外,硬件原型允许精确和实时的评估,但提供有限的灵活性,并且不允许微控制器单元(MCU)的敏捷设计探索。在这项工作中,我们提出了一个基于现场可编程门阵列(FPGA)的边缘计算节点仿真平台。我们的解决方案将可编程逻辑的灵活性和实时性与硬件原型评估相结合。我们提出了一个用于设计探索的开源微控制器架构,它集成了一个活动监视器来收集运行时的痕迹。然后使用这些活动跟踪来分析边缘计算节点中不同组件的能耗。重要的是,我们的FPGA连接到真实的传感器和通信模块,以便在节点评估和探索期间与环境进行交互。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An FPGA-based Emulation Platform for Edge Computing Node Design Exploration
Recent advances in machine learning have made it possible to consider the implementation of smart applications in constrained systems at the edge of the network. These memory and Central Processing Unit (CPU) intensive applications may require specific exploration methodologies to design efficient node computing devices. To better guide and validate these explorations, we need to perform energy and performance evaluations of the system. Software-based evaluation tools are application-oriented and do not consider real-time and hardware constraints. Alternatively, hardware prototyping allows an accurate and real-time evaluation but offers limited flexibility and does not allow agile design exploration of the microcontroller unit (MCU). In this work, we propose a Field Programmable Gate Arrays (FPGA) based edge computing node emulation platform. Our solution combines the flexibility and the real-time capability of programmable logic with hardware prototype evaluation. We present an open-source microcontroller architecture for design exploration which integrates an activity monitor to collect traces at run-time. These activity traces are then used to profile the energy consumption of different components in the edge computing node. Importantly, our FPGA is connected to real sensors and communication modules to enable interactions with the environment during the node evaluation and exploration.
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