{"title":"A framework for the development of protocols","authors":"F. Crazzolara, Giuseppe Milicia","doi":"10.1109/CSD.2003.1207722","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207722","url":null,"abstract":"We present the /spl chi/-Spaces framework, a tool designed to support every step of a security protocol's life cycle. Its integrated development environment (IDE) eases the task of protocol design, debugging and simulation.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On lifting of statechart structuring mechanisms","authors":"L. Gomes, Anikó Costa","doi":"10.1109/CSD.2003.1207715","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207715","url":null,"abstract":"We propose a set of procedures addressing the implementation of statechart models. The main goal of this set of procedures is to lift the structuring mechanisms presented in statecharts to the top level. In this sense, the complexity of statechart implementation will be similar to the complexity of communicating concurrent state machines and the platforms selected to support implementation will not need to have specific capabilities to directly support the structuring mechanisms of Harel's statecharts. The framework is the design of embedded systems (in the sense of reactive realtime systems) and automation applications, either industrial automation or building automation, either the emphasis is on system, hardware or software levels, using or not codesign techniques. An application focused on hardware implementation using VHDL as implementation language is used as an example.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126844811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Paolo Ballarini, L. Capra, G. Franceschinis, M. Pierro
{"title":"Memory fault tolerance software mechanisms: design and configuration support through SWN models","authors":"Paolo Ballarini, L. Capra, G. Franceschinis, M. Pierro","doi":"10.1109/CSD.2003.1207705","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207705","url":null,"abstract":"We present a case study of a software fault tolerance mechanisms, the distributed memory, designed and implemented within the European projects TIRAN and DEPAUDE, and currently under study within the Italian project ISIDE. The studied mechanisms are part of a complete framework of general purpose software fault tolerance mechanisms. We show a method for the compositional construction of models of the DM and of the environment in which it operates, expressed in the stochastic well formed nets (SWN) formalism. Different versions of submodels, at different detail level are presented and compared using some behaviour inheritance notions taken from the literature.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126366960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
L. Petrucci, J. Billington, L. Kristensen, Z. Qureshi
{"title":"Developing a formal specification for the mission system of a maritime surveillance aircraft","authors":"L. Petrucci, J. Billington, L. Kristensen, Z. Qureshi","doi":"10.1109/CSD.2003.1207703","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207703","url":null,"abstract":"The mission system of an aircraft is a complex real-time distributed system consisting of a mission control computer, different kinds of devices interconnected by a number of serial data buses. The complexity and real-time requirements of mission systems have motivated research into the application of formal techniques to investigate and predict the effects of upgrades on mission system behaviour. We report on a joint research project between the University of South Australia and Australia's Defence Science and Technology Organisation. In previous work we modelled a generic avionics mission system with coloured Petri nets and analysed the model using state spaces. Here, we describe how this model was refined and modified to obtain a coloured Petri net model for the AP-3C Orion maritime surveillance aircraft.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129046159","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Detecting state coding conflicts in STG unfoldings using SAT","authors":"Victor Khomenko, M. Koutny, A. Yakovlev","doi":"10.1109/CSD.2003.1207699","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207699","url":null,"abstract":"The behaviour of asynchronous circuits is often described by signal transition graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is that of identifying whether an STG satisfies the complete state coding (CSC) requirement, e.g., by using model checking based on the state graph of an STG. We avoid constructing the state graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. The algorithm is derived by adopting the boolean satisfiability (SAT) approach. This technique leads not only to huge memory savings when compared to methods based on state graphs, but also to significant speedups.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128671845","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Case studies of model checking for embedded system designs","authors":"X. Chen, H. Hsieh, F. Balarin, Yosinori Watanabe","doi":"10.1109/CSD.2003.1207696","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207696","url":null,"abstract":"As modern embedded systems become more integrated and complex, it is crucial to be able to represent systems at multiple levels of abstraction, so that the design space can be effectively explored by successive refinements and abstractions. We present a formal verification methodology and case studies for property verification of designs represented at different abstraction levels. Utilizing Metropolis meta-model (MMM), Y-chart Application Programmer's Interface (YAPI), an automatic translator, and the model checker SPIN, we verify properties for both system level representations and refined representations.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"241 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115596348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Modifying Petri net models by means of crosscutting operations","authors":"J. Barros, L. Gomes","doi":"10.1109/CSD.2003.1207712","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207712","url":null,"abstract":"Increasingly complex abstraction and composition constructs have been proposed for Petri nets, sometimes to the point that the quantity and diversity of net inscriptions seem to obscure the proclaimed advantages of Petri nets graphical representation. These constructs are oriented towards system synthesis but typically overlook the necessity of future model modifications due to unanticipated changes in requirements. These can imply modifications across several of the initially composed modules. We propose the use of two simple composition operations, net addition and net subtraction, that allow the introduction of the necessary modifications without being dependent on the net class or composition constructs in use. The operations can even be used concomitantly with the existent composition constructs. Three application examples are also presented which illustrate the use of the proposed operations in classic settings.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131328640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Verification of JavaSpaces/spl trade/ parallel programs","authors":"J. Pol, M. V. Espada","doi":"10.1109/CSD.2003.1207714","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207714","url":null,"abstract":"We illustrate a formal verification method for distributed JavaSpaces applications by analyzing a nontrivial fault tolerant algorithm that solves a typical coordination problem. The problem consists of the computation of an extensive task, performed in parallel by splitting it into smaller and more manageable parts. The proposed solution, based on JavaSpaces coordination primitives, transactions and timeouts, is verified by translating it to the formal language /spl mu/CRL, together with the previously developed /spl mu/CRL-model of the JavaSpaces architecture, and by using model checking techniques.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"195 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131772822","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Cyclic communicating processes: hierarchy and verification","authors":"P. Thiagarajan","doi":"10.1109/CSD.2003.1207693","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207693","url":null,"abstract":"We advocate Cyclic Communicating Processes (CCPs) as a viable and tractable model of computation for reactive systems. As the name suggests, the model consists of a network of sequential agents that communicate with each other. The crucial restriction is that the control flow of each agent is cyclic. The communication mechanism consists of the agents performing common actions together. The first extension consists of endowing the control states with finite number of colors which can serve as abstractions of the values of the variables owned by the agents. This leads to a restricted class of colored Petri nets that one could term as colored marked graphs or colored T-systems. This class of CCPs has a natural semantics in terms of finite 1-safe Petri nets. We concentrate on specification and verification issues related to branching temporal logics for CCPs.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115088214","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"VoDkaV tool: model checking for extracting global scheduler properties from local restrictions","authors":"J. J. S. Penas, T. Arts","doi":"10.1109/CSD.2003.1207726","DOIUrl":"https://doi.org/10.1109/CSD.2003.1207726","url":null,"abstract":"The VoDka server is a video on demand system developed using Erlang/OTP. We have developed a tool that, taking directly a simple abstraction of the source code of the system, first translates it into a intermediate process algebra and, later, generates the state space of a given configuration of the system. From this state space, some global properties of the system can be extracted. The tool uses internally different translation and model checking tools, and has a prototype GUI for hiding the internal details of the process.","PeriodicalId":228530,"journal":{"name":"Third International Conference on Application of Concurrency to System Design, 2003. Proceedings.","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2003-06-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116509209","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}