{"title":"Using waveform engineering to optimize Class-F power amplifier performance in an envelope tracking architecture","authors":"Z. Mokhti, P. Tasker, J. Lees","doi":"10.1109/EUMC.2014.6986682","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986682","url":null,"abstract":"Achieving optimal efficiency in FET-based power amplifiers used in envelope tracking (ET) architectures can be difficult, mainly due to the dynamic variation of drain-to-source capacitance (Cds) with applied drain voltage. If, for example class-F or inverse class-F high-efficiency modes are used, there is clearly a motivation to maintain devices in high-efficient states, over as much of the dynamic range as possible, where the operating supply voltage varies quite dramatically. In order to identify optimal matching solutions, the optimum fundamental and harmonic impedances need to be determined and understood at different drain voltages (Vds). Using time-domain waveform measurements and active harmonic load-pull at the device current generator plane, this paper analyzes the behavior of the current and voltage waveforms present at the output of a 10W high-voltage laterally diffused metal oxide semiconductor (HVLDMOS) device in an emulated ET setting. The measurement system is used to robustly engineer optimized class-F operation at different drain voltages at an operating frequency of 900MHz. A design methodology is then discussed that allows optimized power amplifier performance for different average Vds, within the operational ET supply voltage range, and the impact this has on overall efficiency.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"106 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125641500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Large-signal characterization of a mixed-signal SoC receiver for multiband SDR/CR designs","authors":"D. Ribeiro, P. Cruz, N. Borges Carvalho","doi":"10.1109/EUMC.2014.6986713","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986713","url":null,"abstract":"This paper shows a framework to evaluate the nonlinear distortion characteristic of a commercial mixed-signal wideband system-on-chip (SoC) receiver. An approach to obtain fully-synchronized amplitude and phase relationships between the analog input and digital output ports is described. Measurement of AM/AM and AM/PM curves under a sinusoidal excitation are executed over a wide input power range, in order to extract device compression information at different carrier frequencies. As well, metrics for the in-band generated nonlinear distortion are obtained by exciting the mixed-signal SoC device with a two-tone signal, and then calculating the respective third-order intermodulation distortion ratio.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"87 36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130363734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A fully integrated CMOS linear power amplifier using an IMD-reduced bias network","authors":"Sungho Lee, Kihyun Kim, Daeyeon Kim","doi":"10.1109/EUMC.2014.6986672","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986672","url":null,"abstract":"A fully integrated CMOS linear RF power amplifier (PA) that includes integrated on-chip input and output matching networks is presented. This PA consists of two-stage configuration, each of which adopts a differential cascode structure. A new gate bias network of the common source amplifier is proposed to suppress intermodulation distortion. The results of the simulation and the measurements of the proposed bias circuit are compared and verified. The PA prototype is fabricated in Dongbu 0.11-μm 1-poly 8-metal CMOS process. The measured results were 29.4 dBm of P-1dB, 34 dB of power gain, a maximum PAE of 40% for a sinusoidal signal, and a peak PAE of 34% for a 900 MHz WCDMA-modulated signal.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"04 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127193500","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An all-pass topology to design a 0–360° continuous phase shifter with low insertion loss and constant differential phase shift","authors":"K. Khoder, M. Le Roy, A. Pérennec","doi":"10.1109/EUMC.2014.6986747","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986747","url":null,"abstract":"In this paper, an analog phase shifter is designed by using a novel all-pass topology. The phase shift can be continuously adjusted from 0 up to 380° by biasing varactor-diodes while maintaining the differential phase shift constant across the 6.7 GHz-7.7 GHz band. This two-stage circuit is simple and compact with respectively insertion losses of 2.9 dB+ 1.3 dB, return losses better than 9.4 dB and a differential phase shift flatness of + 11° in the worst case. With a 90.5°/dB Figure-of-Merit, this topology presents an interesting trade-off between low-cost, low loss, large phase-shift range, phase flatness and bandwidth. Measurements are discussed and carefully compared to current competing topologies.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121037233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Design of a near-field-focused substrate integrated planar array antenna","authors":"Lei Wang, Y. Cheng, F. Xue","doi":"10.1109/EUMIC.2014.6997920","DOIUrl":"https://doi.org/10.1109/EUMIC.2014.6997920","url":null,"abstract":"A X-band multi-layer near-field-focused antenna (NFFA) is developed on the basis of substrate integrated waveguide (SIW) technology and fabricated through PCB process. Several metallic vias with different diameters, which are equivalent to open-ended air-filled circular waveguides, are fabricated to form phase shifters and radiating elements at the same time. They are fed by an SIW wideband feeding network underneath these radiating elements to achieve a compact configuration. Between the radiating and feeding layers, there exists a separated matching layer to achieve a good reflection characteristic. As an example, a 4×4 NFFA prototype is fabricated and measure. The maximum intensity of the electric field is at 150 mm. The measured results are in good agreement with the simulated ones near the focal distance.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123947565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Reconfigurable digital Cartesian feedback for transmitters","authors":"D. Ndong, S. Reed, J. Diouris, B. Feuvrie","doi":"10.1109/EUMC.2014.6986750","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986750","url":null,"abstract":"This paper presents an original method to realize digital loop control for a radio communication V/UHF (Very/Ultra High Frequency) transmitter. The objective is to propose a SDR (Software Defined Radio) solution with a correction of the PA (Power Amplifier) nonlinearities. The proposed architecture is full digital solution except the up-converter for specific reasons. The used numeric core is a Virtex6 FPGA (Field Programmable Gate Array). The down-converter and loop filters are integrated in the digital part. Measurements show improvement of 5% of the EVM (Error Vector Magnitude) and more than 20 dB for the ACPR (Adjacent Channel Power Ratio) compared to the open loop. The overall delay system is about 1.4 μs and the loop gain is 20.4 dB.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115150408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Daniel Markert, C. Haslach, Holger Heimpel, A. Pascht, G. Fischer
{"title":"Phase-modulated DSM-PWM hybrids with pulse length restriction for switch-mode power amplifiers","authors":"Daniel Markert, C. Haslach, Holger Heimpel, A. Pascht, G. Fischer","doi":"10.1109/EUMC.2014.6986698","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986698","url":null,"abstract":"This paper describes a novel concept to encode amplitude and phase information in binary waveforms for switch-mode power amplifiers (SMPAs). A combination of a phase-modulated delta-sigma modulation (DSM) and pulse-width modulation (PWM) makes it possible to adapt signal generation to the power amplifier limits. The proposed system overcomes the inherent signal quality limits of digital systems with fixed clock frequencies by applying a phase modulated clock. We demonstrate that it is possible to achieve the performance of conventional concepts at less than half of the bit rate. Simulation and measurement results are given for important figures of merit of mobile communication signals with high peak-to-average power ratio (PAPR). A proof of concept is implemented in a laboratory setting using a conventional FPGA.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"111 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120982390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
J. Sombrin, P. Michel, G. Soubercaze-Pun, I. Albert
{"title":"Memristors as non-linear behavioral models for passive inter-modulation simulation","authors":"J. Sombrin, P. Michel, G. Soubercaze-Pun, I. Albert","doi":"10.1109/EUMC.2014.6986689","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986689","url":null,"abstract":"We propose to use memristors as memory nonlinear circuits to build behavioral models useful in the simulation of passive inter-modulation in RF and microwave devices such as filters, antennas and in general connections.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121567156","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improved microwave noise performance in 0.15μm AlGaN/AlN/GaN HEMTs on silicon","authors":"G. Ng, S. Arulkumaran, K. Ranjan, S. Vicknesh","doi":"10.1109/EUMC.2014.6986703","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986703","url":null,"abstract":"High-frequency microwave noise performances (2 GHz to 19 GHz) were investigated on AlGaN/AlN/GaN High Electron Mobility Transistors (HEMTs) with 0.15 μm T-gate fabricated on high resistivity 4-inch Silicon. The HEMTs exhibited maximum drain current density (I<sub>Dmax</sub>) of 830 mA/mm, maximum extrinsic transconductance (g<sub>mmax</sub>) of 353 mS/mm, unity current cut-off frequency (f<sub>T</sub>) of 65 GHz and maximum oscillation frequency (f<sub>max</sub>) of 125 GHz. At V<sub>DS</sub>=6V and I<sub>D</sub>=188mA/mm, the devices exhibited a minimum noise figure (NF<sub>min</sub>) of 0.59 dB at 10 GHz and 1.5 dB at 18 GHz. The NF<sub>min</sub> for 10 GHz is the lowest reported value in the literatures for conventional AlGaN/GaN HEMTs on Si substrate. No significant change in microwave noise performance has been observed in the devices over for a wide range of I<sub>D</sub> (22 mA/mm to 500mA/mm) and V<sub>D</sub> (3V to 16V).","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132096352","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Parasitic elements based decoupling technique for monopole four square array antenna","authors":"S. Salama, K. Solbach","doi":"10.1109/EUMC.2014.6986734","DOIUrl":"https://doi.org/10.1109/EUMC.2014.6986734","url":null,"abstract":"An alternative approach to port decoupling for the monopole four square array antenna is proposed. In contrast to the decoupling of the monopole four square array antenna based on eigenmodes theory, port decoupling over wider frequency band is obtained by a proper choice of parasitic elements dimensions and positions for a given array elements spacing without extending the overall area. The decoupled ports of the array may then be matched by using conventional matching circuits.","PeriodicalId":223533,"journal":{"name":"2014 9th European Microwave Integrated Circuit Conference","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115864495","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}