2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)最新文献

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Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter 用片上电压表分析了与正负电源故障相关的故障注入机制
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855583
Loïc Zussa, J. Dutertre, J. Clédière, B. Robisson
{"title":"Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter","authors":"Loïc Zussa, J. Dutertre, J. Clédière, B. Robisson","doi":"10.1109/HST.2014.6855583","DOIUrl":"https://doi.org/10.1109/HST.2014.6855583","url":null,"abstract":"Power supply underpowering and negative power supply glitches are commonly used for the purpose of injecting faults into secure circuits. The related fault injection mechanism has been extensively studied: it is based on setup time violations. Positive power supply glitches are also used to inject faults. However, an increase of the supply voltage is not consistent with a mechanism based on setup time violation. Besides, no research work has yet identified the corresponding mechanism. In this work, we report the use of an embedded delay-meter to monitor the core voltage of a programmable device exposed to power supply glitches. It permitted us to gain a further insight into the mechanism associated with power glitches and also to identify the injection mechanism of positive power supply glitches.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129675853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 22
Side-channel leakage on silicon substrate of CMOS cryptographic chip CMOS密码芯片硅衬底的侧通道泄漏
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855564
Daisuke Fujimoto, Daichi Tanaka, N. Miura, M. Nagata, Yu-ichi Hayashi, N. Homma, S. Bhasin, J. Danger
{"title":"Side-channel leakage on silicon substrate of CMOS cryptographic chip","authors":"Daisuke Fujimoto, Daichi Tanaka, N. Miura, M. Nagata, Yu-ichi Hayashi, N. Homma, S. Bhasin, J. Danger","doi":"10.1109/HST.2014.6855564","DOIUrl":"https://doi.org/10.1109/HST.2014.6855564","url":null,"abstract":"Power supply currents of CMOS digital circuits partly flow through a silicon substrate in their returning (ground) paths. The voltage bounce due to the substrate currents is seen wherever p+ substrate taps on a p-type die and regarded as a substrate noise. An on-chip waveform monitor confirms the side-channel leakage on the silicon substrate from an AES cryptographic module in a 65 nm CMOS demonstrator chip for the first time. The silicon substrate is essentially common to every circuit and inevitably carries the leakage to the observation taps located at the front as well as at the bottom surface of a die, even if the power and ground wires of an AES module are intentionally separated from the other building blocks. Substrate leakage channels may break the hiding of a cryptographic module regarding its location on a die. The physical properties including the distance dependency are experimentally explored.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115069895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A noise bifurcation architecture for linear additive physical functions 线性可加性物理函数的噪声分岔结构
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855582
M. Yu, David M'Raïhi, I. Verbauwhede, S. Devadas
{"title":"A noise bifurcation architecture for linear additive physical functions","authors":"M. Yu, David M'Raïhi, I. Verbauwhede, S. Devadas","doi":"10.1109/HST.2014.6855582","DOIUrl":"https://doi.org/10.1109/HST.2014.6855582","url":null,"abstract":"Physical Unclonable Functions (PUFs) allow a silicon device to be authenticated based on its manufacturing variations using challenge/response evaluations. Popular realizations use linear additive functions as building blocks. Security is scaled up using non-linear mixing (e.g., adding XORs). Because the responses are physically derived and thus noisy, the resulting explosion in noise impacts both the adversary (which is desirable) as well as the verifier (which is undesirable). We present the first architecture for linear additive physical functions where the noise seen by the adversary and the noise seen by the verifier are bifurcated by using a randomized decimation technique and a novel response recovery method at an authentication verification server. We allow the adversary's noise ηa → 0.50 while keeping the verifier's noise ηv constant, using a parameter-based authentication modality that does not require explicit challenge/response pair storage at the server. We present supporting data using 28nm FPGA PUF noise results as well as machine learning attack results. We demonstrate that our architecture can also withstand recent side-channel attacks that filter the noise (to clean up training challenge/response labels) prior to machine learning.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116647310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 73
Side-channel countermeasure for SHA-3 at almost-zero area overhead SHA-3在几乎为零的区域开销下的侧信道对抗
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855576
Mostafa M. I. Taha, P. Schaumont
{"title":"Side-channel countermeasure for SHA-3 at almost-zero area overhead","authors":"Mostafa M. I. Taha, P. Schaumont","doi":"10.1109/HST.2014.6855576","DOIUrl":"https://doi.org/10.1109/HST.2014.6855576","url":null,"abstract":"Keccak is a hashing function selected by NIST as the SHA-3 standard. Keccak provides an interesting opportunity to have a single core that can perform hashing, MAC generation, authenticated encryption and more. For all applications that involve processing of a secret key, side-channel protection should be considered. Indeed, Keccak authors proposed threshold implementations using three and four shares. However, their proposal contradicts using the same core in different applications. Using a threshold implementation for unkeyed application will involve a huge loss of performance (3x to 4x). In this paper, we solve this problem by proposing a countermeasure that employs a new message format and requires only two gates at 3.7 GE. For unkeyed applications, there will be no loss of any kind. For keyed applications, there will be a one-time performance loss that can be trivialized at long message lengths. Our contribution is essential to provide a single core for all the protected and unprotected applications of SHA-3.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125514596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Cryptographically secure shields 加密保护盾
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855563
Jean-Michel Cioranesco, J. Danger, T. Graba, S. Guilley, Y. Mathieu, D. Naccache, X. Ngo
{"title":"Cryptographically secure shields","authors":"Jean-Michel Cioranesco, J. Danger, T. Graba, S. Guilley, Y. Mathieu, D. Naccache, X. Ngo","doi":"10.1109/HST.2014.6855563","DOIUrl":"https://doi.org/10.1109/HST.2014.6855563","url":null,"abstract":"Probing attacks are serious threats on integrated circuits. Security products often include a protective layer called shield that acts like a digital fence. In this article, we demonstrate a new shield structure that is cryptographically secure. This shield is based on the newly proposed SIMON lightweight block cipher and independent mesh lines to ensure the security against probing attacks of the hardware located behind the shield. Such structure can be proven secure against state-of-the-art invasive attacks. For the first time in the open literature, we describe a chip designed with a digital shield, and give an extensive report of its cost, in terms of power, metal layer(s) to sacrifice and of logic (including the logic to connect it to the CPU). Also, we explain how “Through Silicon Vias” (TSV) technology can be used for the protection against both frontside and backside probing.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127561618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Efficient and secure intellectual property (IP) design with split fabrication 高效和安全的知识产权(IP)设计与分裂制造
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855561
Kaushik Vaidyanathan, Renzhi Liu, Ekin Sumbul, Qiuling Zhu, F. Franchetti, Larry Pileggi
{"title":"Efficient and secure intellectual property (IP) design with split fabrication","authors":"Kaushik Vaidyanathan, Renzhi Liu, Ekin Sumbul, Qiuling Zhu, F. Franchetti, Larry Pileggi","doi":"10.1109/HST.2014.6855561","DOIUrl":"https://doi.org/10.1109/HST.2014.6855561","url":null,"abstract":"Split fabrication, the process of splitting an IC into an untrusted and trusted tier, facilitates access to the most advanced semiconductor manufacturing capabilities available in the world without requiring disclosure of design intent. While researchers have investigated the security of logic blocks in the context of split fabrication, the security of IP blocks, another key component of an SoC, has not been examined. Our security analysis of IP block designs, specifically embedded memory and analog components, shows that they are vulnerable to “recognition attacks” at the untrusted foundry due to the use of standardized floorplans and leaf cell layouts. We propose methodologies to design these blocks efficiently and securely, and demonstrate their effectiveness using 130nm split fabricated testchips.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117287260","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 60
A hierarchical formal approach to verifying side-channel resistant cryptographic processors 验证抗侧信道加密处理器的分层形式化方法
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855572
K. Okamoto, N. Homma, T. Aoki, S. Morioka
{"title":"A hierarchical formal approach to verifying side-channel resistant cryptographic processors","authors":"K. Okamoto, N. Homma, T. Aoki, S. Morioka","doi":"10.1109/HST.2014.6855572","DOIUrl":"https://doi.org/10.1109/HST.2014.6855572","url":null,"abstract":"This paper presents a hierarchical formal verification method for cryptographic processors based on a combination of a word-level computer algebra procedure and a bit-level decision procedure using PPRM (Positive Polarity Reed-Muller) expansion. In the proposed method, the entire datapath structure of a cryptographic processor is described in the form of a hierarchical graph . The correctness of the entire circuit function is verified on this graph representation, by the algebraic method, and the function of each component is verified by the PPRM method, respectively. We have applied the proposed verification method to a complicated AES (Advanced Encryption Standard) circuit with a masking countermeasure against side-channel attack. The results show that the proposed method can verify such practical circuit automatically within 4 minutes while the conventional methods fail.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131307780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Robust keys from physical unclonable functions 来自物理不可克隆函数的健壮键
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855575
Merrielle Spain, Benjamin Fuller, K. Ingols, R. Cunningham
{"title":"Robust keys from physical unclonable functions","authors":"Merrielle Spain, Benjamin Fuller, K. Ingols, R. Cunningham","doi":"10.1109/HST.2014.6855575","DOIUrl":"https://doi.org/10.1109/HST.2014.6855575","url":null,"abstract":"Weak physical unclonable functions (PUFs) can instantiate read-proof hardware tokens (Tuyls et al. 2006, CHES) where benign variation, such as changing temperature, yields a consistent key, but invasive attempts to learn the key destroy it. Previous approaches evaluate security by measuring how much an invasive attack changes the derived key (Pappu et al. 2002, Science). If some attack insufficiently changes the derived key, an expert must redesign the hardware. An unexplored alternative uses software to enhance token response to known physical attacks. Our approach draws on machine learning. We propose a variant of linear discriminant analysis (LDA), called PUF LDA, which reduces noise levels in PUF instances while enhancing changes from known attacks. We compare PUF LDA with standard techniques using an optical coating PUF and the following feature types: raw pixels, fast Fourier transform, short-time Fourier transform, and wavelets. We measure the true positive rate for valid detection at a 0% false positive rate (no mistakes on samples taken after an attack). PUF LDA improves the true positive rate from 50% on average (with a large variance across PUFs) to near 100%. While a well-designed physical process is irreplaceable, PUF LDA enables system designers to improve the PUF reliability-security tradeoff by incorporating attacks without redesigning the hardware token.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124613773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Increasing the efficiency of laser fault injections using fast gate level reverse engineering 利用快速栅级逆向工程提高激光故障注入效率
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855569
Franck Courbon, Philippe Loubet-Moundi, J. Fournier, A. Tria
{"title":"Increasing the efficiency of laser fault injections using fast gate level reverse engineering","authors":"Franck Courbon, Philippe Loubet-Moundi, J. Fournier, A. Tria","doi":"10.1109/HST.2014.6855569","DOIUrl":"https://doi.org/10.1109/HST.2014.6855569","url":null,"abstract":"Laser fault injections have been evolving rapidly with the advent of more precise, sophisticated and cost-efficient sources, optics and control circuits. In this paper, we show a methodology to improve the test coverage and to speed up analysis based on laser fault injections by only targeting standard cells of interest. We describe how to identify interesting spatial positions thanks to the use of some chemicals along with an automated Scanning Electron Microscope image acquisition, alignment and processing. Using the latter information, fault injections with a high success rate have been obtained against a hardware implemented AES module using a laser beam. With such tools and methodology, we show that attacks become much faster.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"239 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114213013","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Split-fabrication obfuscation: Metrics and techniques 分裂制造混淆:度量和技术
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855560
Meenatchi Jagasivamani, P. Gadfort, Michel Sika, M. Bajura, M. Fritze
{"title":"Split-fabrication obfuscation: Metrics and techniques","authors":"Meenatchi Jagasivamani, P. Gadfort, Michel Sika, M. Bajura, M. Fritze","doi":"10.1109/HST.2014.6855560","DOIUrl":"https://doi.org/10.1109/HST.2014.6855560","url":null,"abstract":"Split-fabrication has been proposed as an approach for secure and trusted access to advanced microelectronics manufacturing capability using un-trusted sources. Each wafer to be manufactured is processed by two semiconductor foundries, combining the front-end capabilities of an advanced but untrusted semiconductor foundry with the back-end capabilities a trusted semiconductor foundry. Since the security of split fabrication relates directly to a front-end foundry's ability to interpret the partial circuit designs it receives, metrics are needed to evaluate the obfuscation of these designs as well as circuit design techniques to alter these metrics. This paper quantitatively examines several “front-end” obfuscation techniques and metrics inspired by information theory, and evaluates their impact on design effort, area, and performance penalties.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123940675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
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