Analysis of the fault injection mechanism related to negative and positive power supply glitches using an on-chip voltmeter

Loïc Zussa, J. Dutertre, J. Clédière, B. Robisson
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引用次数: 22

Abstract

Power supply underpowering and negative power supply glitches are commonly used for the purpose of injecting faults into secure circuits. The related fault injection mechanism has been extensively studied: it is based on setup time violations. Positive power supply glitches are also used to inject faults. However, an increase of the supply voltage is not consistent with a mechanism based on setup time violation. Besides, no research work has yet identified the corresponding mechanism. In this work, we report the use of an embedded delay-meter to monitor the core voltage of a programmable device exposed to power supply glitches. It permitted us to gain a further insight into the mechanism associated with power glitches and also to identify the injection mechanism of positive power supply glitches.
用片上电压表分析了与正负电源故障相关的故障注入机制
电源供电不足和负电源故障通常用于向安全电路注入故障。相关的故障注入机制已经得到了广泛的研究:它是基于设置时间违规的。正电源故障也用于注入故障。然而,电源电压的增加与基于设置时间违反的机制不一致。此外,还没有研究工作确定相应的机制。在这项工作中,我们报告了使用嵌入式延迟计来监测暴露于电源故障的可编程器件的核心电压。它使我们能够进一步深入了解与电源故障相关的机制,并确定正电源故障的注入机制。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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