2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)最新文献

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Power supply glitch attacks: Design and evaluation of detection circuits 电源故障攻击:检测电路的设计与评估
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855584
Kamil Gomina, J. Rigaud, P. Gendrier, P. Candelier, A. Tria
{"title":"Power supply glitch attacks: Design and evaluation of detection circuits","authors":"Kamil Gomina, J. Rigaud, P. Gendrier, P. Candelier, A. Tria","doi":"10.1109/HST.2014.6855584","DOIUrl":"https://doi.org/10.1109/HST.2014.6855584","url":null,"abstract":"Techniques using modification of power supplies to attack circuits do not require strong expertise or expensive equipment. Supply voltage glitches are then a serious threat to the security of electronic devices. In this paper, mechanisms involved during such attacks are analyzed and described. It is shown that timing properties of logic gates are very sensitive to power glitches and can be used to inject faults. For this reason, detection circuits which monitor timing properties of dedicated paths are designed to detect glitch attacks. To validate these solutions, a new approach based on the study of propagation delay variation is also presented. Following this approach, the performance of detection circuits can be evaluated at design level using a standard digital design flow.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115374662","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA 复合PUF: FPGA上物理不可克隆功能的新设计范式
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855567
D. Sahoo, Sayandeep Saha, Debdeep Mukhopadhyay, R. Chakraborty, Hitesh Kapoor
{"title":"Composite PUF: A new design paradigm for Physically Unclonable Functions on FPGA","authors":"D. Sahoo, Sayandeep Saha, Debdeep Mukhopadhyay, R. Chakraborty, Hitesh Kapoor","doi":"10.1109/HST.2014.6855567","DOIUrl":"https://doi.org/10.1109/HST.2014.6855567","url":null,"abstract":"Physically Unclonable Function (PUF) designs proposed in the recent literature vary widely in diverse characteristics such as hardware resource requirement, reliability, entropy, and robustness against mathematical cloning. Most of the standalone PUF designs suffer from either poor performance profile or unacceptable resource-overhead. We present a novel PUF design paradigm, termed as PUF Composition, that utilizes smaller PUFs as design building blocks to define a “Composite PUF” having larger challenge-space and superior performance profile at reasonable resource-overhead. A formal framework for PUF composition based on a probabilistic model has also been developed to enable the Composite PUF designer to have a-priori estimate of the relative qualities of several composite PUF options, without actually implementing them physically. The notion of PUF composition, and the probabilistic model developed for delay-PUFs, have both been validated using Ring Oscillator PUF (ROPUF) and Arbiter PUF (APUF) on Xilinx Spartan-3 Field Programmable Gate Array (FPGA).","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114769252","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 57
Countering the effects of silicon aging on SRAM PUFs 对抗硅老化对SRAM puf的影响
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855586
Roel Maes, Vincent van der Leest
{"title":"Countering the effects of silicon aging on SRAM PUFs","authors":"Roel Maes, Vincent van der Leest","doi":"10.1109/HST.2014.6855586","DOIUrl":"https://doi.org/10.1109/HST.2014.6855586","url":null,"abstract":"Silicon aging, in particular NBTI, causes many PUFs to exhibit a natural tendency of growing less reliable over time. This is inconvenient or even unacceptable for in-the-field applications. In case of SRAM PUFs it is observed that the impact of NBTI aging depends on the data stored in the SRAM. In this work, we investigate the effects of data-dependent silicon aging on SRAM PUF reliability under a number of realistic scenarios. In an accelerated aging experiment on a 65nm CMOS SRAM PUF implementation it is observed that many scenarios cause a smaller reliability reduction than natural aging. Some scenarios even show anti-aging effects, i.e. they cause the SRAM PUF to grow more reliable over time. This is a significant improvement when using an SRAM PUF. Even more so because data-dependent (anti-)aging has a particularly low overhead, requiring neither any changes to the PUF circuit nor any pre-deployment effort.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130029124","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
A frequency leakage model for SCA SCA的频率泄漏模型
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855577
S. Tiran, S. Ordas, Y. Teglia, M. Agoyan, P. Maurine
{"title":"A frequency leakage model for SCA","authors":"S. Tiran, S. Ordas, Y. Teglia, M. Agoyan, P. Maurine","doi":"10.1109/HST.2014.6855577","DOIUrl":"https://doi.org/10.1109/HST.2014.6855577","url":null,"abstract":"This paper introduces a leakage model in the frequency domain to enhance the efficiency of Side Channel Attacks of CMOS circuits. While usual techniques are focused on noise removal around clock harmonics, we show that the actual leakage is not necessary located in those expected bandwidths as experimentally observed by E. Mateos and C.H. Gebotys in 2010. We start by building a theoretical modeling of power consumption and electromagnetic emanations before deriving from it a criterion to guide standard attacks. This criterion is then validated on real experiments, both on FPGA and ASIC, showing an impressive increase of the yield of SCA.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134304684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Entropy loss in PUF-based key generation schemes: The repetition code pitfall 基于puf的密钥生成方案中的熵损失:重复码缺陷
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855566
Patrick Koeberl, Jiangtao Li, Anand Rajan, Wei Wu
{"title":"Entropy loss in PUF-based key generation schemes: The repetition code pitfall","authors":"Patrick Koeberl, Jiangtao Li, Anand Rajan, Wei Wu","doi":"10.1109/HST.2014.6855566","DOIUrl":"https://doi.org/10.1109/HST.2014.6855566","url":null,"abstract":"One of the promising usages of Physically Unclonable Functions (PUFs) is to generate cryptographic keys from PUFs for secure storage of key material. This usage has attractive properties such as physical unclonability and enhanced resistance against hardware attacks. In order to extract a reliable cryptographic key from a noisy PUF response a fuzzy extractor is used to convert non-uniform random PUF responses into nearly uniform randomness. Bösch et al. in 2008 proposed a fuzzy extractor suitable for efficient hardware implementation using two-stage concatenated codes, where the inner stage is a conventional error correcting code and the outer stage is a repetition code. In this paper we show that the combination of PUFs with repetition code approaches is not without risk and must be approached carefully. For example, PUFs with min-entropy lower than 66% may yield zero leftover entropy in the generated key for some repetition code configurations. In addition, we find that many of the fuzzy extractor designs in the literature are too optimistic with respect to entropy estimation. For high security applications, we recommend a conservative estimation of entropy loss based on the theoretical work of fuzzy extractors and present parameters for generating 128-bit keys from memory based PUFs.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115878511","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 56
New scan attacks against state-of-the-art countermeasures and DFT 针对最先进的对抗措施和DFT的新扫描攻击
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855585
Subidh Ali, O. Sinanoglu, S. Saeed, R. Karri
{"title":"New scan attacks against state-of-the-art countermeasures and DFT","authors":"Subidh Ali, O. Sinanoglu, S. Saeed, R. Karri","doi":"10.1109/HST.2014.6855585","DOIUrl":"https://doi.org/10.1109/HST.2014.6855585","url":null,"abstract":"Scan attack has been known as a threat to Design for Testability (DFT). All the existing attacks require both the normal mode and the test mode of the device. In normal mode the intermediate results of a crypto-hardware are captured in scan chains and in the test mode the results are shifted out. One simple countermeasure for this kind of attacks is to reset the device whenever there is a switch of the mode. A recent test-mode-only attack shows that the mode-reset countermeasure is insecure against scan attack. An attack is still possible using only the test mode of the device. However, the attack was presented without the presence of an on-chip test compactor. In this paper we propose a new test-mode-only attack on AES hardware which works in the presence of an on-chip response compactor. The proposed attack retrieves the secret key with negligible time complexity. The attack results show that DFT infrastructures with response compactor are vulnerable to scan attack even in the presence of mode-reset countermeasure.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122031961","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Optimality and beyond: The case of 4×4 S-boxes 最优性及超越:4×4 S-boxes的例子
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855573
S. Picek, Baris Ege, K. Papagiannopoulos, L. Batina, D. Jakobović
{"title":"Optimality and beyond: The case of 4×4 S-boxes","authors":"S. Picek, Baris Ege, K. Papagiannopoulos, L. Batina, D. Jakobović","doi":"10.1109/HST.2014.6855573","DOIUrl":"https://doi.org/10.1109/HST.2014.6855573","url":null,"abstract":"S-boxes with better transparency order are expected to have higher side-channel resistance. For 8×8 S-boxes this is not practical, considering the costs of lookup-table implementations and deterioration of many properties like nonlinearity or delta uniformity. However, if we concentrate on the 4×4 S-box size we can observe that it is possible to obtain S-boxes with better transparency order while maintaining proper “classical” properties. To prove this, we experiment with PRINCE and PRESENT S-boxes. We use various methods and show that evolutionary algorithms are also viable in obtaining the lowest known transparency order value for the nonlinearity value of 4. Next, we show that affine transformation changes the transparency order while keeping “classical” properties intact. By using this technique, it is possible to generate optimal S-boxes with improved DPA-related properties.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129067574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
NREPO: Normal basis Recomputing with Permuted Operands 使用置换操作数的正常基重计算
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855581
Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, R. Karri
{"title":"NREPO: Normal basis Recomputing with Permuted Operands","authors":"Xiaofei Guo, Debdeep Mukhopadhyay, Chenglu Jin, R. Karri","doi":"10.1109/HST.2014.6855581","DOIUrl":"https://doi.org/10.1109/HST.2014.6855581","url":null,"abstract":"Hardware implementations of cryptographic algorithms are vulnerable to natural and malicious faults. Concurrent Error Detection (CED) can be used to detect these faults. We present NREPO, a CED which does not require redundant computational resources in the design. Therefore, one can integrate it when computational resources are scarce or when the redundant resources are difficult to harness for CED. We integrate NREPO in a low-cost Advanced Encryption Standard (AES) implementation with 8-bit datapath. We show that NREPO has 25 and 50 times lower fault miss rate than robust code and parity, respectively. The area, throughput, and power are compared with other CEDs on 45nm ASIC. The hardware overhead of NREPO is 34.9%. The throughput and power are 271.6Mbps and 1579.3μW, respectively. One can also implement NREPO in other cryptographic algorithms.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114035055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
On design of a highly secure PUF based on non-linear current mirrors 基于非线性电流镜的高安全PUF设计
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855565
Raghavan Kumar, W. Burleson
{"title":"On design of a highly secure PUF based on non-linear current mirrors","authors":"Raghavan Kumar, W. Burleson","doi":"10.1109/HST.2014.6855565","DOIUrl":"https://doi.org/10.1109/HST.2014.6855565","url":null,"abstract":"Physically Unclonable Functions (PUFs) are lightweight hardware security primitives for generating unique signatures from the unpredictable nature of silicon. However, most of the proposed PUFs have been shown to be vulnerable to modeling attacks, especially against Machine Learning algorithms. A subset of challenge-response pairs can leak the required information to break a PUF due to the presence of a linear separating boundary between the PUF responses. In this paper, we propose a strong and secure PUF based on non-linear current mirrors. The fundamental idea is to propagate a current through two identical chains of non-linear current mirrors. The current through a single stage is shifted by some amount based on the strength of the input current. As the current shift is not a fixed value anymore, strong non-linearity is introduced into the challenge-response relationship. The proposed PUF shows excellent properties upon statistical circuit simulation. The average inter-distance and intra-distance of the proposed PUF are 49.9% and 0.8% respectively. One of the most striking features of the proposed PUF is the low information leakage measured in terms of its modeling attack resistance. By employing Support Vector Machine (SVM) based attacks, we observed that the proposed PUF is almost 10-30x stronger than the delay-based PUFs. Moreover, the current mode nature of the PUF circuit enables low power operation. The proposed PUF consumes about 15% lower energy than an arbiter PUF to produce a single response bit.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"2011 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121007207","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 98
Verification of untrusted chips using trusted layout and emission measurements 使用可信的布局和发射测量验证不可信的芯片
2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) Pub Date : 2014-05-06 DOI: 10.1109/HST.2014.6855562
F. Stellari, P. Song, A. Weger, Jim Culp, A. Herbert, D. Pfeiffer
{"title":"Verification of untrusted chips using trusted layout and emission measurements","authors":"F. Stellari, P. Song, A. Weger, Jim Culp, A. Herbert, D. Pfeiffer","doi":"10.1109/HST.2014.6855562","DOIUrl":"https://doi.org/10.1109/HST.2014.6855562","url":null,"abstract":"This paper presents a novel methodology for hardware security and Trojan detection applications. The method is based on our proposed tester-based optical methodology that combines different test patterns, time-integrated and time-resolved emission measurements to localize gates, detect logic states, and identify functional block activity inside a chip in a non-invasive fashion. A detailed application example using a 90 nm bulk digital test chip shows that emission images can be effectively used to identify unexpected and missing emission signatures that may be related to chip alterations.","PeriodicalId":222932,"journal":{"name":"2014 IEEE International Symposium on Hardware-Oriented Security and Trust (HOST)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-05-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125078007","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
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