{"title":"Dynamic Patching of Embedded Software","authors":"M. Ekman, Henrik Thane","doi":"10.1109/RTAS.2007.10","DOIUrl":"https://doi.org/10.1109/RTAS.2007.10","url":null,"abstract":"In this paper, we present a method for patching embedded multitasking real-time systems applications during runtime, for instrumentation purposes. The method uses binary modification techniques and automates the entire patch process. The method makes it possible to insert and remove instrumentation code without preparing the original source code. The method makes it possible to invoke code patches during run-time, without having to rely on dynamic linking of object files, or predeployment prepared dormant code. The actual modification of the executing target binary is performed in a safe and controlled manner by a dedicated low interference mutation task","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114603791","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hijack: Taking Control of COTS Systems for Real-Time User-Level Services","authors":"Gabriel Parmer, R. West","doi":"10.1109/RTAS.2007.14","DOIUrl":"https://doi.org/10.1109/RTAS.2007.14","url":null,"abstract":"This paper focuses on a technique to empower commercial-off-the-shelf (COTS) systems with an execution environment, and corresponding services, to support real-time and embedded applications. By leveraging COTS systems, we are able to reduce the potentially expensive maintenance and development costs of proprietary solutions. We describe a system called \"Hijack\" that enables user-level services to take control of features such as CPU scheduling, interrupt handling and synchronization. In contrast to other approaches that support real-time tasks within the kernel of commodity systems such as Linux, Hijack provides the basis for predictable thread execution at user-level. No changes to the kernel source code are required to support this approach. Instead, Hijack works by using a combination of kernel module support and an interposed execution environment between traditional process address spaces and the kernel. This technique enables system calls and hardware interrupts to be intercepted with bounded latencies via the kernel module, that passes control to a user-level real-time executive. From within the executive, system-wide services and policies can be deployed to over-ride certain features of the underlying kernel, while still leveraging base kernel services where appropriate. Using this technique, we show how a vanilla Linux system can be hijacked to support predictable service execution using a series of user-defined policies. In particular, we show how to deliver and process asynchronous events with bounded latency, using interposition agents within a Hijack execution environment. Results show that for realtime streaming applications, Hijack is able to receive and process packets with significantly lower loss rates and jitter compared to using alternative application-level processes for the same task","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123218812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimizing the FPGA Implementation of HRT Systems","authors":"M. Natale, Enrico Bini","doi":"10.1109/RTAS.2007.25","DOIUrl":"https://doi.org/10.1109/RTAS.2007.25","url":null,"abstract":"The availability of programmable hardware devices with high density of logic elements and the possibility of implementing CPUs (called softcores) using a fraction of the FPGA area offers additional flexibility for the implementation of embedded applications with real-time constraints. When implementing functions on such devices, designers can choose between hardware and software. Also, the designer can select the number of CPUs that must be created to best support the execution of the real-time software. In this paper, we define a design optimization procedure for hard real-time systems, in which each functional block can be implemented in HW, using the logic elements available on the FPGA, or in SW, by means of a real-time task executed by a softcore. The optimizer allocates the functions and the softcores such that the HW implemented part is mapped within the area constraints and the software part is allocated so that schedulability can be guaranteed. When feasible solutions exist, the minimum utilization solution is computed","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125073189","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. D. Bui, R. Pellizzoni, M. Caccamo, C. Cheah, A. Tzakis
{"title":"Soft Real-Time Chains for Multi-Hop Wireless Ad-Hoc Networks","authors":"B. D. Bui, R. Pellizzoni, M. Caccamo, C. Cheah, A. Tzakis","doi":"10.1109/RTAS.2007.34","DOIUrl":"https://doi.org/10.1109/RTAS.2007.34","url":null,"abstract":"Prioritized MAC protocols are needed to support soft real-time communication in wireless networks. In this paper, we introduce real-time chain, a new prioritized MAC protocol to support soft real-time data flows in multi-hop wireless ad-hoc networks. By avoiding packet collisions and limiting the effect of priority inversions, real-time chain is able to provide soft real-time and bandwidth guarantees. Furthermore, the use of multiple channels enables high spatial reuse and transmission rates. Finally, our approach can be integrated with a slightly modified version of the IEEE 802.15.4 standard. The protocol has been fully implemented on Crossbow MICAz hardware and its performance has been validated with a large set of both indoor and outdoor experiments","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"62 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120919293","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal Unified Data Allocation and Task Scheduling for Real-Time Multi-Tasking Systems","authors":"R. Ghattas, Gregory S. Parsons, A. Dean","doi":"10.1109/RTAS.2007.23","DOIUrl":"https://doi.org/10.1109/RTAS.2007.23","url":null,"abstract":"Many real-time (RT) embedded systems can benefit from a memory hierarchy to bridge the processor/memory speed gap. These RT embedded systems usually utilize a cacheless architecture to avoid the time variability which complicates the timing analysis essential for RT systems. In the absence of a cache the burden of allocating the data objects to the memory hierarchy is on the programmer/compiler. There has been much research into allocating data objects into the memory hierarchy for efficient execution. However, existing methods have limited scope and ignore some aspects of RT multitasking embedded systems. In this paper we propose a synergistic, optimal approach to allocating data objects and scheduling real-time tasks for embedded systems. We allocate data using integer linear programming (ILP) to minimize each task's worst-case execution time (WCET), then perform preemption threshold scheduling (PTS) on the tasks to reduce stack memory requirements while still meeting hard RT deadlines. The memory reduction of PTS allows these steps to be repeated. The data objects now require less memory, so more can fit into faster memory, further reducing WCET. The increased slack time can be used by PTS to reduce preemptions further, until a fixed point is reached. We evaluate the technique with several levels of data object granularity using both synthetic workloads and a real-time benchmark and find it to be highly effective","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123821987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Dynamic Task Scheduling and Processing Element Allocation for Multi-Function SoCs","authors":"Ya-Shu Chen, C. Shih, Tei-Wei Kuo","doi":"10.1109/RTAS.2007.11","DOIUrl":"https://doi.org/10.1109/RTAS.2007.11","url":null,"abstract":"This work is motivated by the rapid increasing of the design complexity of many embedded systems. It aims at the proposing of solutions to resolve the hardware contention issues of non-preemptive processing elements shared among tasks and the cost optimization. A software solution based on the starting time management is proposed to interleave task executions on processing elements. Algorithms are proposed to determine the required processing elements of selected types, when there is no knowledge on the releasing time of any task: When task release orders are known a priori, an optimal algorithm is presented if processing elements have the same cost; otherwise, a pseudo-polynomial-time algorithm based on dynamic programming is presented for optimal solutions. The performance of the algorithms is also evaluated for general cases","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124173410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Prioritized SMT Architecture with IPC Control Method for Real-Time Processing","authors":"N. Yamasaki, Ikuo Magaki, T. Itou","doi":"10.1109/RTAS.2007.28","DOIUrl":"https://doi.org/10.1109/RTAS.2007.28","url":null,"abstract":"This paper describes a novel processor architecture, the prioritized SMT architecture with the IPC control method, to guarantee the execution time of real-time threads. Based on priority set by a real-time scheduler, all hardware resources including cache systems, fetch, issue, and execution units, are controlled, so that our processor can execute multiple threads in real-time. All runnable threads are simultaneously executed as much as possible in priority order, so that the execution order becomes congruent with the priority order set by a real-time scheduler. If a resource conflict occurs, the lower priority threads are kept waiting until the higher priority thread finishes using the resource. In brief, context switching required for real-time scheduling and execution is converted to the prioritized SMT execution. Here, some triggers including cache misses and branch prediction misses fluctuate the execution speed of a thread. Additionally, in case of an SMT processor, the execution time of each thread may vary according to a combination of simultaneous executing threads. To guarantee the execution time of real-time threads accurately, the IPC control method that monitors and controls each thread IPC in a feedback loop is designed and implemented. Our IPC control method can keep the IPC deviation of the thread within plusmn1% bounds, if the target IPC is less than 80% of the single thread execution IPC. Our processor is implemented as a processing core of a system LSI, which process was TSMC 0.13 mum 8 layered Cu wiring, used for distributed real-time systems including humanoid robots, bilateral robots, embedded control systems, and ubiquitous computing systems","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125159326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Real-Time Divisible Load Scheduling for Cluster Computing","authors":"Xuan Lin, Ying Lu, J. Deogun, S. Goddard","doi":"10.1109/RTAS.2007.29","DOIUrl":"https://doi.org/10.1109/RTAS.2007.29","url":null,"abstract":"Cluster computing has emerged as a new paradigm for solving large-scale problems. To enhance QoS and provide performance guarantees in cluster computing environments, various real-time scheduling algorithms and workload models have been investigated. Computational loads that can be arbitrarily divided into independent pieces represent many real-world applications. Divisible load theory (DLT) provides insight into distribution strategies for such computations. However, the problem of providing performance guarantees to divisible load applications has not yet been systematically studied. This paper investigates such algorithms for a cluster environment. Design parameters that affect the performance of these algorithms and scenarios when the choice of these parameters have significant effects are studied. A novel algorithmic approach integrating DLT and EDF (earliest deadline first) scheduling is proposed. For comparison, we also propose a heuristic algorithm. Intensive experimental results show that the application of DLT to real-time cluster-based scheduling leads to significantly better scheduling approaches","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115069351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Natale, Wei Zheng, C. Pinello, P. Giusto, A. Sangiovanni-Vincentelli
{"title":"Optimizing End-to-End Latencies by Adaptation of the Activation Events in Distributed Automotive Systems","authors":"M. Natale, Wei Zheng, C. Pinello, P. Giusto, A. Sangiovanni-Vincentelli","doi":"10.1109/RTAS.2007.24","DOIUrl":"https://doi.org/10.1109/RTAS.2007.24","url":null,"abstract":"Schedulability theory provides support for the analysis of the worst case latencies in distributed computations when the architecture of the system is known and the communication and synchronization mechanisms have been defined. In the design of complex automotive systems, however, a great benefit of schedulability analysis may come from its use as an aid in the exploration of the software architecture configurations that can best support the target application. We present an optimization algorithm that leverages the trade-offs between the purely periodic and the data-driven activation models to meet the latency requirements of distributed vehicle functions. We demonstrate its effectiveness on a complex automotive architecture","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127619259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal Static Task Scheduling on Reconfigurable Hardware Devices Using Model-Checking","authors":"Z. Gu, Mingxuan Yuan, Xiuqiang He","doi":"10.1109/RTAS.2007.22","DOIUrl":"https://doi.org/10.1109/RTAS.2007.22","url":null,"abstract":"Real-time scheduling for FPGAs presents unique challenges to traditional real-time scheduling theory, since it is similar to, but more general than multi-processor scheduling. In his paper, we address two problems of static task scheduling on a partially runtime reconfigurable FPGA: finding an optimal static schedule for a task graph with the optimization objective of minimizing the total schedule length, and finding a feasible static schedule for a set of periodic tasks within a hyper-period with the objective of meeting all deadlines. We model the multi-tasking system with timed automata and use reachability analysis of the UPPAAL model-checker to explore the design space and find an optimal or feasible schedule","PeriodicalId":222543,"journal":{"name":"13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127263546","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}